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104-powerpc-mpc85xx-change-P2020RDB-dts-file-for-OpenWRT.patch 3.9 KB

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  1. From 93514afd769c305182beeed1f9c4c46235879ef8 Mon Sep 17 00:00:00 2001
  2. From: Pawel Dembicki <[email protected]>
  3. Date: Sun, 30 Dec 2018 23:24:41 +0100
  4. Subject: [PATCH] powerpc: mpc85xx: change P2020RDB dts file for OpenWRT
  5. This patch apply chages for OpenWRT in P2020RDB
  6. dts file.
  7. Signed-off-by: Pawel Dembicki <[email protected]>
  8. ---
  9. arch/powerpc/boot/dts/fsl/p2020rdb.dts | 98 +++++++++++++++++---------
  10. 1 file changed, 63 insertions(+), 35 deletions(-)
  11. --- a/arch/powerpc/boot/dts/fsl/p2020rdb.dts
  12. +++ b/arch/powerpc/boot/dts/fsl/p2020rdb.dts
  13. @@ -5,10 +5,15 @@
  14. * Copyright 2009-2012 Freescale Semiconductor Inc.
  15. */
  16. +/dts-v1/;
  17. +
  18. /include/ "p2020si-pre.dtsi"
  19. +#include <dt-bindings/gpio/gpio.h>
  20. +#include <dt-bindings/input/input.h>
  21. +
  22. / {
  23. - model = "fsl,P2020RDB";
  24. + model = "Freescale P2020RDB";
  25. compatible = "fsl,P2020RDB";
  26. aliases {
  27. @@ -34,48 +39,38 @@
  28. 0x2 0x0 0x0 0xffb00000 0x00020000>;
  29. nor@0,0 {
  30. - #address-cells = <1>;
  31. - #size-cells = <1>;
  32. compatible = "cfi-flash";
  33. reg = <0x0 0x0 0x1000000>;
  34. bank-width = <2>;
  35. device-width = <1>;
  36. - partition@0 {
  37. - /* This location must not be altered */
  38. - /* 256KB for Vitesse 7385 Switch firmware */
  39. - reg = <0x0 0x00040000>;
  40. - label = "NOR (RO) Vitesse-7385 Firmware";
  41. - read-only;
  42. - };
  43. -
  44. - partition@40000 {
  45. - /* 256KB for DTB Image */
  46. - reg = <0x00040000 0x00040000>;
  47. - label = "NOR (RO) DTB Image";
  48. - read-only;
  49. - };
  50. + partitions {
  51. + compatible = "fixed-partitions";
  52. + #address-cells = <1>;
  53. + #size-cells = <1>;
  54. - partition@80000 {
  55. - /* 3.5 MB for Linux Kernel Image */
  56. - reg = <0x00080000 0x00380000>;
  57. - label = "NOR (RO) Linux Kernel Image";
  58. - read-only;
  59. - };
  60. + partition@0 {
  61. + /* This location must not be altered */
  62. + /* 256KB for Vitesse 7385 Switch firmware */
  63. + reg = <0x0 0x00040000>;
  64. + label = "NOR (RO) Vitesse-7385 Firmware";
  65. + read-only;
  66. + };
  67. - partition@400000 {
  68. - /* 11MB for JFFS2 based Root file System */
  69. - reg = <0x00400000 0x00b00000>;
  70. - label = "NOR (RW) JFFS2 Root File System";
  71. - };
  72. + partition@40000 {
  73. + compatible = "denx,fit";
  74. + reg = <0x00040000 0x00ec0000>;
  75. + label = "firmware";
  76. + };
  77. - partition@f00000 {
  78. - /* This location must not be altered */
  79. - /* 512KB for u-boot Bootloader Image */
  80. - /* 512KB for u-boot Environment Variables */
  81. - reg = <0x00f00000 0x00100000>;
  82. - label = "NOR (RO) U-Boot Image";
  83. - read-only;
  84. + partition@f00000 {
  85. + /* This location must not be altered */
  86. + /* 512KB for u-boot Bootloader Image */
  87. + /* 512KB for u-boot Environment Variables */
  88. + reg = <0x00f00000 0x00100000>;
  89. + label = "u-boot";
  90. + read-only;
  91. + };
  92. };
  93. };
  94. @@ -85,6 +80,7 @@
  95. compatible = "fsl,p2020-fcm-nand",
  96. "fsl,elbc-fcm-nand";
  97. reg = <0x1 0x0 0x40000>;
  98. + nand-ecc-mode = "none";
  99. partition@0 {
  100. /* This location must not be altered */
  101. @@ -140,13 +136,43 @@
  102. soc: soc@ffe00000 {
  103. ranges = <0x0 0x0 0xffe00000 0x100000>;
  104. + gpio0: gpio-controller@fc00 {
  105. + };
  106. +
  107. i2c@3000 {
  108. + temperature-sensor@4c {
  109. + compatible = "adi,adt7461";
  110. + reg = <0x4c>;
  111. + };
  112. +
  113. + eeprom@50 {
  114. + compatible = "atmel,24c256";
  115. + reg = <0x50>;
  116. + };
  117. +
  118. rtc@68 {
  119. compatible = "dallas,ds1339";
  120. reg = <0x68>;
  121. };
  122. };
  123. + i2c@3100 {
  124. + pmic@11 {
  125. + compatible = "zl2006";
  126. + reg = <0x11>;
  127. + };
  128. +
  129. + gpio@18 {
  130. + compatible = "nxp,pca9557";
  131. + reg = <0x18>;
  132. + };
  133. +
  134. + eeprom@52 {
  135. + compatible = "atmel,24c01";
  136. + reg = <0x52>;
  137. + };
  138. + };
  139. +
  140. spi@7000 {
  141. flash@0 {
  142. #address-cells = <1>;
  143. @@ -200,10 +226,12 @@
  144. phy0: ethernet-phy@0 {
  145. interrupts = <3 1 0 0>;
  146. reg = <0x0>;
  147. + reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
  148. };
  149. phy1: ethernet-phy@1 {
  150. interrupts = <3 1 0 0>;
  151. reg = <0x1>;
  152. + reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
  153. };
  154. tbi-phy@2 {
  155. device_type = "tbi-phy";