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- From 47e161a7873b0891f4e01a69a839f6161d816ea8 Mon Sep 17 00:00:00 2001
- From: Robert Marko <[email protected]>
- Date: Wed, 25 Oct 2023 14:57:57 +0530
- Subject: [PATCH] cpufreq: qcom-nvmem: add support for IPQ6018
- IPQ6018 SoC series comes in multiple SKU-s, and not all of them support
- high frequency OPP points.
- SoC itself does however have a single bit in QFPROM to indicate the CPU
- speed-bin.
- That bit is used to indicate frequency limit of 1.5GHz, but that alone is
- not enough as IPQ6000 only goes up to 1.2GHz, but SMEM ID can be used to
- limit it further.
- IPQ6018 compatible is blacklisted from DT platdev as the cpufreq device
- will get created by NVMEM CPUFreq driver.
- Signed-off-by: Robert Marko <[email protected]>
- [ Viresh: Fixed rebase conflict. ]
- Signed-off-by: Viresh Kumar <[email protected]>
- ---
- drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
- drivers/cpufreq/qcom-cpufreq-nvmem.c | 58 ++++++++++++++++++++++++++++
- 2 files changed, 59 insertions(+)
- --- a/drivers/cpufreq/cpufreq-dt-platdev.c
- +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
- @@ -163,6 +163,7 @@ static const struct of_device_id blockli
- { .compatible = "ti,dra7", },
- { .compatible = "ti,omap3", },
-
- + { .compatible = "qcom,ipq6018", },
- { .compatible = "qcom,ipq8064", },
- { .compatible = "qcom,apq8064", },
- { .compatible = "qcom,msm8974", },
- --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
- +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
- @@ -31,6 +31,8 @@
-
- #include <dt-bindings/arm/qcom,ids.h>
-
- +#define IPQ6000_VERSION BIT(2)
- +
- struct qcom_cpufreq_drv;
-
- struct qcom_cpufreq_match_data {
- @@ -204,6 +206,57 @@ len_error:
- return ret;
- }
-
- +static int qcom_cpufreq_ipq6018_name_version(struct device *cpu_dev,
- + struct nvmem_cell *speedbin_nvmem,
- + char **pvs_name,
- + struct qcom_cpufreq_drv *drv)
- +{
- + u32 msm_id;
- + int ret;
- + u8 *speedbin;
- + *pvs_name = NULL;
- +
- + ret = qcom_smem_get_soc_id(&msm_id);
- + if (ret)
- + return ret;
- +
- + speedbin = nvmem_cell_read(speedbin_nvmem, NULL);
- + if (IS_ERR(speedbin))
- + return PTR_ERR(speedbin);
- +
- + switch (msm_id) {
- + case QCOM_ID_IPQ6005:
- + case QCOM_ID_IPQ6010:
- + case QCOM_ID_IPQ6018:
- + case QCOM_ID_IPQ6028:
- + /* Fuse Value Freq BIT to set
- + * ---------------------------------
- + * 2’b0 No Limit BIT(0)
- + * 2’b1 1.5 GHz BIT(1)
- + */
- + drv->versions = 1 << (unsigned int)(*speedbin);
- + break;
- + case QCOM_ID_IPQ6000:
- + /*
- + * IPQ6018 family only has one bit to advertise the CPU
- + * speed-bin, but that is not enough for IPQ6000 which
- + * is only rated up to 1.2GHz.
- + * So for IPQ6000 manually set BIT(2) based on SMEM ID.
- + */
- + drv->versions = IPQ6000_VERSION;
- + break;
- + default:
- + dev_err(cpu_dev,
- + "SoC ID %u is not part of IPQ6018 family, limiting to 1.2GHz!\n",
- + msm_id);
- + drv->versions = IPQ6000_VERSION;
- + break;
- + }
- +
- + kfree(speedbin);
- + return 0;
- +}
- +
- static const struct qcom_cpufreq_match_data match_data_kryo = {
- .get_version = qcom_cpufreq_kryo_name_version,
- };
- @@ -218,6 +271,10 @@ static const struct qcom_cpufreq_match_d
- .genpd_names = qcs404_genpd_names,
- };
-
- +static const struct qcom_cpufreq_match_data match_data_ipq6018 = {
- + .get_version = qcom_cpufreq_ipq6018_name_version,
- +};
- +
- static int qcom_cpufreq_probe(struct platform_device *pdev)
- {
- struct qcom_cpufreq_drv *drv;
- @@ -362,6 +419,7 @@ static const struct of_device_id qcom_cp
- { .compatible = "qcom,apq8096", .data = &match_data_kryo },
- { .compatible = "qcom,msm8996", .data = &match_data_kryo },
- { .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
- + { .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 },
- { .compatible = "qcom,ipq8064", .data = &match_data_krait },
- { .compatible = "qcom,apq8064", .data = &match_data_krait },
- { .compatible = "qcom,msm8974", .data = &match_data_krait },
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