| 1234567891011121314151617181920212223242526272829303132 |
- From 3b48a7d925a757b3fa53c04baaf68bb8313c3ffb Mon Sep 17 00:00:00 2001
- From: Kathiravan Thirumoorthy <[email protected]>
- Date: Thu, 14 Sep 2023 12:29:58 +0530
- Subject: [PATCH] arm64: dts: qcom: ipq8074: include the GPLL0 as clock
- provider for mailbox
- While the kernel is booting up, APSS PLL will be running at 800MHz with
- GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be
- configured to the rate based on the opp table and the source also will
- be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0,
- with this inclusion, CPU Freq correctly reports that CPU is running at
- 800MHz rather than 24MHz.
- Signed-off-by: Kathiravan Thirumoorthy <[email protected]>
- Reviewed-by: Konrad Dybcio <[email protected]>
- ---
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
- --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
- +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
- @@ -685,8 +685,8 @@
- compatible = "qcom,ipq8074-apcs-apps-global",
- "qcom,ipq6018-apcs-apps-global";
- reg = <0x0b111000 0x1000>;
- - clocks = <&a53pll>, <&xo>;
- - clock-names = "pll", "xo";
- + clocks = <&a53pll>, <&xo>, <&gcc GPLL0>;
- + clock-names = "pll", "xo", "gpll0";
-
- #clock-cells = <1>;
- #mbox-cells = <1>;
|
