0059-v6.9-arm64-dts-qcom-ipq6018-add-thermal-zones.patch 4.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180
  1. From 8f053e5616352943e16966f195f5a7a161e6fe7d Mon Sep 17 00:00:00 2001
  2. From: Mantas Pucka <[email protected]>
  3. Date: Thu, 25 Jan 2024 11:04:12 +0200
  4. Subject: [PATCH] arm64: dts: qcom: ipq6018: add thermal zones
  5. Add thermal zones to make use of thermal sensors data. For CPU zone,
  6. add cooling device that uses CPU frequency scaling.
  7. Signed-off-by: Mantas Pucka <[email protected]>
  8. Link: https://lore.kernel.org/r/[email protected]
  9. Signed-off-by: Bjorn Andersson <[email protected]>
  10. ---
  11. arch/arm64/boot/dts/qcom/ipq6018.dtsi | 121 ++++++++++++++++++++++++++
  12. 1 file changed, 121 insertions(+)
  13. --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
  14. +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
  15. @@ -9,6 +9,7 @@
  16. #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
  17. #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
  18. #include <dt-bindings/clock/qcom,apss-ipq.h>
  19. +#include <dt-bindings/thermal/thermal.h>
  20. / {
  21. #address-cells = <2>;
  22. @@ -43,6 +44,7 @@
  23. clock-names = "cpu";
  24. operating-points-v2 = <&cpu_opp_table>;
  25. cpu-supply = <&ipq6018_s2>;
  26. + #cooling-cells = <2>;
  27. };
  28. CPU1: cpu@1 {
  29. @@ -55,6 +57,7 @@
  30. clock-names = "cpu";
  31. operating-points-v2 = <&cpu_opp_table>;
  32. cpu-supply = <&ipq6018_s2>;
  33. + #cooling-cells = <2>;
  34. };
  35. CPU2: cpu@2 {
  36. @@ -67,6 +70,7 @@
  37. clock-names = "cpu";
  38. operating-points-v2 = <&cpu_opp_table>;
  39. cpu-supply = <&ipq6018_s2>;
  40. + #cooling-cells = <2>;
  41. };
  42. CPU3: cpu@3 {
  43. @@ -79,6 +83,7 @@
  44. clock-names = "cpu";
  45. operating-points-v2 = <&cpu_opp_table>;
  46. cpu-supply = <&ipq6018_s2>;
  47. + #cooling-cells = <2>;
  48. };
  49. L2_0: l2-cache {
  50. @@ -888,6 +893,122 @@
  51. };
  52. };
  53. + thermal-zones {
  54. + nss-top-thermal {
  55. + polling-delay-passive = <250>;
  56. + polling-delay = <1000>;
  57. + thermal-sensors = <&tsens 4>;
  58. +
  59. + trips {
  60. + nss-top-critical {
  61. + temperature = <125000>;
  62. + hysteresis = <1000>;
  63. + type = "critical";
  64. + };
  65. + };
  66. + };
  67. +
  68. + nss-thermal {
  69. + polling-delay-passive = <250>;
  70. + polling-delay = <1000>;
  71. + thermal-sensors = <&tsens 5>;
  72. +
  73. + trips {
  74. + nss-critical {
  75. + temperature = <125000>;
  76. + hysteresis = <1000>;
  77. + type = "critical";
  78. + };
  79. + };
  80. + };
  81. +
  82. + wcss-phya0-thermal {
  83. + polling-delay-passive = <250>;
  84. + polling-delay = <1000>;
  85. + thermal-sensors = <&tsens 7>;
  86. +
  87. + trips {
  88. + wcss-phya0-critical {
  89. + temperature = <125000>;
  90. + hysteresis = <1000>;
  91. + type = "critical";
  92. + };
  93. + };
  94. + };
  95. +
  96. + wcss-phya1-thermal {
  97. + polling-delay-passive = <250>;
  98. + polling-delay = <1000>;
  99. + thermal-sensors = <&tsens 8>;
  100. +
  101. + trips {
  102. + wcss-phya1-critical {
  103. + temperature = <125000>;
  104. + hysteresis = <1000>;
  105. + type = "critical";
  106. + };
  107. + };
  108. + };
  109. +
  110. + cpu-thermal {
  111. + polling-delay-passive = <250>;
  112. + polling-delay = <1000>;
  113. + thermal-sensors = <&tsens 13>;
  114. +
  115. + trips {
  116. + cpu-critical {
  117. + temperature = <125000>;
  118. + hysteresis = <1000>;
  119. + type = "critical";
  120. + };
  121. +
  122. + cpu_alert: cpu-passive {
  123. + temperature = <110000>;
  124. + hysteresis = <1000>;
  125. + type = "passive";
  126. + };
  127. + };
  128. +
  129. + cooling-maps {
  130. + map0 {
  131. + trip = <&cpu_alert>;
  132. + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  133. + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  134. + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  135. + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  136. + };
  137. + };
  138. + };
  139. +
  140. + lpass-thermal {
  141. + polling-delay-passive = <250>;
  142. + polling-delay = <1000>;
  143. + thermal-sensors = <&tsens 14>;
  144. +
  145. + trips {
  146. + lpass-critical {
  147. + temperature = <125000>;
  148. + hysteresis = <1000>;
  149. + type = "critical";
  150. + };
  151. + };
  152. + };
  153. +
  154. + ddrss-top-thermal {
  155. + polling-delay-passive = <250>;
  156. + polling-delay = <1000>;
  157. + thermal-sensors = <&tsens 15>;
  158. +
  159. + trips {
  160. + ddrss-top-critical {
  161. + temperature = <125000>;
  162. + hysteresis = <1000>;
  163. + type = "critical";
  164. + };
  165. + };
  166. + };
  167. + };
  168. +
  169. timer {
  170. compatible = "arm,armv8-timer";
  171. interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,