mt7981b-dlink-aquila-pro-ai-m30-a1.dts 5.0 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /dts-v1/;
  3. #include "mt7981.dtsi"
  4. / {
  5. model = "D-Link AQUILA PRO AI M30 A1";
  6. compatible = "dlink,aquila-pro-ai-m30-a1", "mediatek,mt7981";
  7. aliases {
  8. label-mac-device = &gmac0;
  9. led-boot = &led_status_white;
  10. led-failsafe = &led_status_red;
  11. led-running = &led_status_white;
  12. led-upgrade = &led_status_blue;
  13. serial0 = &uart0;
  14. };
  15. chosen {
  16. stdout-path = "serial0:115200n8";
  17. };
  18. gpio-keys {
  19. compatible = "gpio-keys";
  20. button-reset {
  21. label = "reset";
  22. linux,code = <KEY_RESTART>;
  23. gpios = <&pio 0 GPIO_ACTIVE_LOW>;
  24. };
  25. button-wps {
  26. label = "wps";
  27. linux,code = <KEY_WPS_BUTTON>;
  28. gpios = <&pio 1 GPIO_ACTIVE_LOW>;
  29. };
  30. button-leds-on-off {
  31. label = "leds-on-off";
  32. linux,code = <KEY_LIGHTS_TOGGLE>;
  33. gpios = <&pio 4 GPIO_ACTIVE_LOW>;
  34. };
  35. };
  36. };
  37. &uart0 {
  38. status = "okay";
  39. };
  40. &watchdog {
  41. status = "okay";
  42. };
  43. &eth {
  44. pinctrl-names = "default";
  45. pinctrl-0 = <&mdio_pins>;
  46. status = "okay";
  47. gmac0: mac@0 {
  48. compatible = "mediatek,eth-mac";
  49. reg = <0>;
  50. phy-mode = "2500base-x";
  51. nvmem-cells = <&macaddr_odm 1>;
  52. nvmem-cell-names = "mac-address";
  53. fixed-link {
  54. speed = <2500>;
  55. full-duplex;
  56. pause;
  57. };
  58. };
  59. gmac1: mac@1 {
  60. compatible = "mediatek,eth-mac";
  61. reg = <1>;
  62. phy-mode = "gmii";
  63. phy-handle = <&int_gbe_phy>;
  64. label = "internet";
  65. nvmem-cells = <&macaddr_odm 0>;
  66. nvmem-cell-names = "mac-address";
  67. };
  68. };
  69. &mdio_bus {
  70. switch: switch@1f {
  71. compatible = "mediatek,mt7531";
  72. reg = <31>;
  73. reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
  74. ports {
  75. #address-cells = <1>;
  76. #size-cells = <0>;
  77. port@0 {
  78. reg = <0>;
  79. label = "lan1";
  80. };
  81. port@1 {
  82. reg = <1>;
  83. label = "lan2";
  84. };
  85. port@2 {
  86. reg = <2>;
  87. label = "lan3";
  88. };
  89. port@3 {
  90. reg = <3>;
  91. label = "lan4";
  92. };
  93. port@6 {
  94. reg = <6>;
  95. label = "cpu";
  96. ethernet = <&gmac0>;
  97. phy-mode = "2500base-x";
  98. fixed-link {
  99. speed = <2500>;
  100. full-duplex;
  101. pause;
  102. };
  103. };
  104. };
  105. };
  106. };
  107. &spi0 {
  108. pinctrl-names = "default";
  109. pinctrl-0 = <&spi0_flash_pins>;
  110. status = "okay";
  111. spi_nand@0 {
  112. compatible = "spi-nand";
  113. #address-cells = <1>;
  114. #size-cells = <1>;
  115. reg = <0>;
  116. spi-max-frequency = <52000000>;
  117. spi-tx-bus-width = <4>;
  118. spi-rx-bus-width = <4>;
  119. mediatek,nmbm;
  120. mediatek,bmt-max-ratio = <1>;
  121. mediatek,bmt-max-reserved-blocks = <64>;
  122. partitions {
  123. compatible = "fixed-partitions";
  124. #address-cells = <1>;
  125. #size-cells = <1>;
  126. partition@0 {
  127. label = "BL2";
  128. reg = <0x00 0x100000>;
  129. read-only;
  130. };
  131. partition@100000 {
  132. label = "u-boot-env";
  133. reg = <0x100000 0x80000>;
  134. };
  135. partition@180000 {
  136. label = "Factory";
  137. reg = <0x180000 0x200000>;
  138. read-only;
  139. nvmem-layout {
  140. compatible = "fixed-layout";
  141. #address-cells = <1>;
  142. #size-cells = <1>;
  143. eeprom_factory_0: eeprom@0 {
  144. reg = <0x0 0x1000>;
  145. };
  146. };
  147. };
  148. partition@380000 {
  149. label = "FIP";
  150. reg = <0x380000 0x200000>;
  151. read-only;
  152. };
  153. partition@580000 {
  154. label = "ubi";
  155. reg = <0x580000 0x3200000>;
  156. };
  157. partition@3780000 {
  158. label = "ubi1";
  159. reg = <0x3780000 0x3200000>;
  160. read-only;
  161. };
  162. partition@6980000 {
  163. label = "Odm";
  164. reg = <0x6980000 0x40000>;
  165. read-only;
  166. nvmem-layout {
  167. compatible = "fixed-layout";
  168. #address-cells = <1>;
  169. #size-cells = <1>;
  170. macaddr_odm: macaddr@81 {
  171. compatible = "mac-base";
  172. reg = <0x81 0x6>;
  173. #nvmem-cell-cells = <1>;
  174. };
  175. };
  176. };
  177. partition@69c0000 {
  178. label = "Config1";
  179. reg = <0x69c0000 0x80000>;
  180. read-only;
  181. };
  182. partition@6a40000 {
  183. label = "Config2";
  184. reg = <0x6a40000 0x80000>;
  185. read-only;
  186. };
  187. partition@6ac0000 {
  188. label = "Storage";
  189. reg = <0x6ac0000 0xA00000>;
  190. read-only;
  191. };
  192. };
  193. };
  194. };
  195. &pio {
  196. spi0_flash_pins: spi0-pins {
  197. mux {
  198. function = "spi";
  199. groups = "spi0", "spi0_wp_hold";
  200. };
  201. conf-pu {
  202. pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
  203. drive-strength = <MTK_DRIVE_8mA>;
  204. bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
  205. };
  206. conf-pd {
  207. pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
  208. drive-strength = <MTK_DRIVE_8mA>;
  209. bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
  210. };
  211. };
  212. i2c_pins_g0: i2c-pins-g0 {
  213. mux {
  214. function = "i2c";
  215. groups = "i2c0_1";
  216. };
  217. };
  218. };
  219. &wifi {
  220. status = "okay";
  221. nvmem-cells = <&eeprom_factory_0>, <&macaddr_odm 2>;
  222. nvmem-cell-names = "eeprom", "mac-address";
  223. };
  224. &i2c0 {
  225. status = "okay";
  226. pinctrl-names = "default";
  227. pinctrl-0 = <&i2c_pins_g0>;
  228. gca230718@40 {
  229. compatible = "unknown,gca230718";
  230. reg = <0x40>;
  231. led_status_red: led@0 {
  232. color = <LED_COLOR_ID_RED>;
  233. function = LED_FUNCTION_STATUS;
  234. reg = <0>;
  235. };
  236. led@1 {
  237. color = <LED_COLOR_ID_GREEN>;
  238. function = LED_FUNCTION_STATUS;
  239. reg = <1>;
  240. };
  241. led_status_blue: led@2 {
  242. color = <LED_COLOR_ID_BLUE>;
  243. function = LED_FUNCTION_STATUS;
  244. reg = <2>;
  245. };
  246. led_status_white: led@3 {
  247. color = <LED_COLOR_ID_WHITE>;
  248. function = LED_FUNCTION_STATUS;
  249. reg = <3>;
  250. };
  251. };
  252. };