DB-WRT01.dts 1.5 KB

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  1. /dts-v1/;
  2. #include "mt7620a.dtsi"
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/input/input.h>
  5. / {
  6. compatible = "planex,db-wrt01", "ralink,mt7620a-soc";
  7. model = "Planex DB-WRT01";
  8. gpio-leds {
  9. compatible = "gpio-leds";
  10. power {
  11. label = "db-wrt01:orange:power";
  12. gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
  13. };
  14. };
  15. gpio-keys-polled {
  16. compatible = "gpio-keys-polled";
  17. #address-cells = <1>;
  18. #size-cells = <0>;
  19. poll-interval = <20>;
  20. s1 {
  21. label = "wps";
  22. gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
  23. linux,code = <KEY_WPS_BUTTON>;
  24. };
  25. };
  26. };
  27. &gpio1 {
  28. status = "okay";
  29. };
  30. &spi0 {
  31. status = "okay";
  32. m25p80@0 {
  33. #address-cells = <1>;
  34. #size-cells = <1>;
  35. compatible = "jedec,spi-nor";
  36. reg = <0>;
  37. spi-max-frequency = <10000000>;
  38. partition@0 {
  39. label = "u-boot";
  40. reg = <0x0 0x30000>;
  41. read-only;
  42. };
  43. partition@30000 {
  44. label = "u-boot-env";
  45. reg = <0x30000 0x10000>;
  46. read-only;
  47. };
  48. factory: partition@40000 {
  49. label = "factory";
  50. reg = <0x40000 0x10000>;
  51. read-only;
  52. };
  53. partition@50000 {
  54. label = "firmware";
  55. reg = <0x50000 0x7b0000>;
  56. };
  57. };
  58. };
  59. &pinctrl {
  60. state_default: pinctrl0 {
  61. gpio {
  62. ralink,group = "i2c", "spi refclk", "rgmii1";
  63. ralink,function = "gpio";
  64. };
  65. };
  66. };
  67. &ethernet {
  68. pinctrl-names = "default";
  69. pinctrl-0 = <&ephy_pins>;
  70. mtd-mac-address = <&factory 0x4>;
  71. mediatek,portmap = "llllw";
  72. };
  73. &gsw {
  74. mediatek,port4 = "ephy";
  75. };
  76. &wmac {
  77. ralink,mtd-eeprom = <&factory 0>;
  78. };
  79. &pcie {
  80. status = "okay";
  81. };