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- From b3b1177092d4d2ba6df74042d39aa42c5055f687 Mon Sep 17 00:00:00 2001
- From: Phil Elwell <[email protected]>
- Date: Mon, 3 Jul 2023 09:08:16 +0100
- Subject: [PATCH] ASoC: dwc: Add DMACR handling
- Add control of the DMACR register, which is required for paced DMA
- (i.e. DREQ) support.
- Signed-off-by: Phil Elwell <[email protected]>
- ---
- sound/soc/dwc/dwc-i2s.c | 13 ++++++++++---
- sound/soc/dwc/local.h | 13 +++++++++++++
- 2 files changed, 23 insertions(+), 3 deletions(-)
- --- a/sound/soc/dwc/dwc-i2s.c
- +++ b/sound/soc/dwc/dwc-i2s.c
- @@ -185,9 +185,9 @@ static void i2s_stop(struct dw_i2s_dev *
-
- static void dw_i2s_config(struct dw_i2s_dev *dev, int stream)
- {
- - u32 ch_reg;
- struct i2s_clk_config_data *config = &dev->config;
- -
- + u32 ch_reg;
- + u32 dmacr = 0;
-
- i2s_disable_channels(dev, stream);
-
- @@ -198,15 +198,22 @@ static void dw_i2s_config(struct dw_i2s_
- i2s_write_reg(dev->i2s_base, TFCR(ch_reg),
- dev->fifo_th - 1);
- i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
- + dmacr |= (DMACR_DMAEN_TXCH0 << ch_reg);
- } else {
- i2s_write_reg(dev->i2s_base, RCR(ch_reg),
- dev->xfer_resolution);
- i2s_write_reg(dev->i2s_base, RFCR(ch_reg),
- dev->fifo_th - 1);
- i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
- + dmacr |= (DMACR_DMAEN_RXCH0 << ch_reg);
- }
- -
- }
- + if (stream == SNDRV_PCM_STREAM_PLAYBACK)
- + dmacr |= DMACR_DMAEN_TX;
- + else if (stream == SNDRV_PCM_STREAM_CAPTURE)
- + dmacr |= DMACR_DMAEN_RX;
- +
- + i2s_write_reg(dev->i2s_base, DMACR, dmacr);
- }
-
- static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
- --- a/sound/soc/dwc/local.h
- +++ b/sound/soc/dwc/local.h
- @@ -25,6 +25,8 @@
- #define RXFFR 0x014
- #define TXFFR 0x018
-
- +#define DMACR 0x200
- +
- /* Interrupt status register fields */
- #define ISR_TXFO BIT(5)
- #define ISR_TXFE BIT(4)
- @@ -47,6 +49,17 @@
- #define RFF(x) (0x40 * x + 0x050)
- #define TFF(x) (0x40 * x + 0x054)
-
- +#define DMACR_DMAEN_TX BIT(17)
- +#define DMACR_DMAEN_RX BIT(16)
- +#define DMACR_DMAEN_TXCH3 BIT(11)
- +#define DMACR_DMAEN_TXCH2 BIT(10)
- +#define DMACR_DMAEN_TXCH1 BIT(9)
- +#define DMACR_DMAEN_TXCH0 BIT(8)
- +#define DMACR_DMAEN_RXCH3 BIT(3)
- +#define DMACR_DMAEN_RXCH2 BIT(2)
- +#define DMACR_DMAEN_RXCH1 BIT(1)
- +#define DMACR_DMAEN_RXCH0 BIT(0)
- +
- /* I2SCOMPRegisters */
- #define I2S_COMP_PARAM_2 0x01F0
- #define I2S_COMP_PARAM_1 0x01F4
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