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036-v6.5-0001-ARM-dts-BCM5301X-Relicense-Rafa-s-code-to-the-GPL-2..patch 10 KB

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  1. From 915fac07f053418d0ab9075af64da2872ca8a7f8 Mon Sep 17 00:00:00 2001
  2. From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <[email protected]>
  3. Date: Wed, 3 May 2023 14:16:10 +0200
  4. Subject: [PATCH] =?UTF-8?q?ARM:=20dts:=20BCM5301X:=20Relicense=20Rafa?=
  5. =?UTF-8?q?=C5=82's=20code=20to=20the=20GPL=202.0+=20/=20MIT?=
  6. MIME-Version: 1.0
  7. Content-Type: text/plain; charset=UTF-8
  8. Content-Transfer-Encoding: 8bit
  9. All BCM5301X device DTS files use dual licensing. Try the same for SoC.
  10. Introduce a new .dtsi file with a proper SPDX tag.
  11. Signed-off-by: Rafał Miłecki <[email protected]>
  12. Link: https://lore.kernel.org/r/[email protected]
  13. Signed-off-by: Florian Fainelli <[email protected]>
  14. ---
  15. MAINTAINERS | 1 +
  16. arch/arm/boot/dts/bcm-ns.dtsi | 202 ++++++++++++++++++++++++++++++++
  17. arch/arm/boot/dts/bcm5301x.dtsi | 192 +-----------------------------
  18. 3 files changed, 205 insertions(+), 190 deletions(-)
  19. create mode 100644 arch/arm/boot/dts/bcm-ns.dtsi
  20. --- a/MAINTAINERS
  21. +++ b/MAINTAINERS
  22. @@ -3579,6 +3579,7 @@ M: Rafał Miłecki <[email protected]>
  23. M: [email protected]
  24. L: [email protected] (moderated for non-subscribers)
  25. S: Maintained
  26. +F: arch/arm/boot/dts/bcm-ns.dtsi
  27. F: arch/arm/boot/dts/bcm470*
  28. F: arch/arm/boot/dts/bcm5301*
  29. F: arch/arm/boot/dts/bcm953012*
  30. --- /dev/null
  31. +++ b/arch/arm/boot/dts/bcm-ns.dtsi
  32. @@ -0,0 +1,202 @@
  33. +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  34. +
  35. +#include <dt-bindings/clock/bcm-nsp.h>
  36. +#include <dt-bindings/gpio/gpio.h>
  37. +#include <dt-bindings/input/input.h>
  38. +#include <dt-bindings/interrupt-controller/irq.h>
  39. +#include <dt-bindings/interrupt-controller/arm-gic.h>
  40. +
  41. +/ {
  42. + axi@18000000 {
  43. + compatible = "brcm,bus-axi";
  44. + reg = <0x18000000 0x1000>;
  45. + ranges = <0x00000000 0x18000000 0x00100000>;
  46. + #address-cells = <1>;
  47. + #size-cells = <1>;
  48. +
  49. + chipcommon: chipcommon@0 {
  50. + reg = <0x00000000 0x1000>;
  51. +
  52. + gpio-controller;
  53. + #gpio-cells = <2>;
  54. + };
  55. +
  56. + pcie0: pcie@12000 {
  57. + reg = <0x00012000 0x1000>;
  58. + };
  59. +
  60. + pcie1: pcie@13000 {
  61. + reg = <0x00013000 0x1000>;
  62. + };
  63. +
  64. + usb2: usb2@21000 {
  65. + reg = <0x00021000 0x1000>;
  66. +
  67. + #address-cells = <1>;
  68. + #size-cells = <1>;
  69. + ranges;
  70. +
  71. + interrupt-parent = <&gic>;
  72. +
  73. + ehci: usb@21000 {
  74. + #usb-cells = <0>;
  75. +
  76. + compatible = "generic-ehci";
  77. + reg = <0x00021000 0x1000>;
  78. + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
  79. + phys = <&usb2_phy>;
  80. +
  81. + #address-cells = <1>;
  82. + #size-cells = <0>;
  83. +
  84. + ehci_port1: port@1 {
  85. + reg = <1>;
  86. + #trigger-source-cells = <0>;
  87. + };
  88. +
  89. + ehci_port2: port@2 {
  90. + reg = <2>;
  91. + #trigger-source-cells = <0>;
  92. + };
  93. + };
  94. +
  95. + ohci: usb@22000 {
  96. + #usb-cells = <0>;
  97. +
  98. + compatible = "generic-ohci";
  99. + reg = <0x00022000 0x1000>;
  100. + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
  101. +
  102. + #address-cells = <1>;
  103. + #size-cells = <0>;
  104. +
  105. + ohci_port1: port@1 {
  106. + reg = <1>;
  107. + #trigger-source-cells = <0>;
  108. + };
  109. +
  110. + ohci_port2: port@2 {
  111. + reg = <2>;
  112. + #trigger-source-cells = <0>;
  113. + };
  114. + };
  115. + };
  116. +
  117. + usb3: usb3@23000 {
  118. + reg = <0x00023000 0x1000>;
  119. +
  120. + #address-cells = <1>;
  121. + #size-cells = <1>;
  122. + ranges;
  123. +
  124. + interrupt-parent = <&gic>;
  125. +
  126. + xhci: usb@23000 {
  127. + #usb-cells = <0>;
  128. +
  129. + compatible = "generic-xhci";
  130. + reg = <0x00023000 0x1000>;
  131. + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
  132. + phys = <&usb3_phy>;
  133. + phy-names = "usb";
  134. +
  135. + #address-cells = <1>;
  136. + #size-cells = <0>;
  137. +
  138. + xhci_port1: port@1 {
  139. + reg = <1>;
  140. + #trigger-source-cells = <0>;
  141. + };
  142. + };
  143. + };
  144. + };
  145. +
  146. + mdio: mdio@18003000 {
  147. + compatible = "brcm,iproc-mdio";
  148. + reg = <0x18003000 0x8>;
  149. + #size-cells = <0>;
  150. + #address-cells = <1>;
  151. + };
  152. +
  153. + dmu-bus@1800c000 {
  154. + compatible = "simple-bus";
  155. + ranges = <0 0x1800c000 0x1000>;
  156. + #address-cells = <1>;
  157. + #size-cells = <1>;
  158. +
  159. + cru-bus@100 {
  160. + compatible = "brcm,ns-cru", "simple-mfd";
  161. + reg = <0x100 0x1a4>;
  162. + ranges;
  163. + #address-cells = <1>;
  164. + #size-cells = <1>;
  165. +
  166. + usb2_phy: phy@164 {
  167. + compatible = "brcm,ns-usb2-phy";
  168. + reg = <0x164 0x4>;
  169. + brcm,syscon-clkset = <&cru_clkset>;
  170. + clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
  171. + clock-names = "phy-ref-clk";
  172. + #phy-cells = <0>;
  173. + };
  174. +
  175. + cru_clkset: syscon@180 {
  176. + compatible = "brcm,cru-clkset", "syscon";
  177. + reg = <0x180 0x4>;
  178. + };
  179. +
  180. + pinctrl: pinctrl@1c0 {
  181. + compatible = "brcm,bcm4708-pinmux";
  182. + reg = <0x1c0 0x24>;
  183. + reg-names = "cru_gpio_control";
  184. +
  185. + spi-pins {
  186. + groups = "spi_grp";
  187. + function = "spi";
  188. + };
  189. +
  190. + pinmux_i2c: i2c-pins {
  191. + groups = "i2c_grp";
  192. + function = "i2c";
  193. + };
  194. +
  195. + pinmux_pwm: pwm-pins {
  196. + groups = "pwm0_grp", "pwm1_grp",
  197. + "pwm2_grp", "pwm3_grp";
  198. + function = "pwm";
  199. + };
  200. +
  201. + pinmux_uart1: uart1-pins {
  202. + groups = "uart1_grp";
  203. + function = "uart1";
  204. + };
  205. + };
  206. +
  207. + thermal: thermal@2c0 {
  208. + compatible = "brcm,ns-thermal";
  209. + reg = <0x2c0 0x10>;
  210. + #thermal-sensor-cells = <0>;
  211. + };
  212. + };
  213. + };
  214. +
  215. + thermal-zones {
  216. + cpu_thermal: cpu-thermal {
  217. + polling-delay-passive = <0>;
  218. + polling-delay = <1000>;
  219. + coefficients = <(-556) 418000>;
  220. + thermal-sensors = <&thermal>;
  221. +
  222. + trips {
  223. + cpu-crit {
  224. + temperature = <125000>;
  225. + hysteresis = <0>;
  226. + type = "critical";
  227. + };
  228. + };
  229. +
  230. + cooling-maps {
  231. + };
  232. + };
  233. + };
  234. +};
  235. --- a/arch/arm/boot/dts/bcm5301x.dtsi
  236. +++ b/arch/arm/boot/dts/bcm5301x.dtsi
  237. @@ -8,11 +8,7 @@
  238. * Licensed under the GNU/GPL. See COPYING for details.
  239. */
  240. -#include <dt-bindings/clock/bcm-nsp.h>
  241. -#include <dt-bindings/gpio/gpio.h>
  242. -#include <dt-bindings/input/input.h>
  243. -#include <dt-bindings/interrupt-controller/irq.h>
  244. -#include <dt-bindings/interrupt-controller/arm-gic.h>
  245. +#include "bcm-ns.dtsi"
  246. / {
  247. #address-cells = <1>;
  248. @@ -149,12 +145,6 @@
  249. };
  250. axi@18000000 {
  251. - compatible = "brcm,bus-axi";
  252. - reg = <0x18000000 0x1000>;
  253. - ranges = <0x00000000 0x18000000 0x00100000>;
  254. - #address-cells = <1>;
  255. - #size-cells = <1>;
  256. -
  257. #interrupt-cells = <1>;
  258. interrupt-map-mask = <0x000fffff 0xffff>;
  259. interrupt-map =
  260. @@ -228,108 +218,15 @@
  261. <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
  262. <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  263. - chipcommon: chipcommon@0 {
  264. - reg = <0x00000000 0x1000>;
  265. -
  266. - gpio-controller;
  267. - #gpio-cells = <2>;
  268. + chipcommon@0 {
  269. interrupt-controller;
  270. #interrupt-cells = <2>;
  271. };
  272. - pcie0: pcie@12000 {
  273. - reg = <0x00012000 0x1000>;
  274. - };
  275. -
  276. - pcie1: pcie@13000 {
  277. - reg = <0x00013000 0x1000>;
  278. - };
  279. -
  280. pcie2: pcie@14000 {
  281. reg = <0x00014000 0x1000>;
  282. };
  283. - usb2: usb2@21000 {
  284. - reg = <0x00021000 0x1000>;
  285. -
  286. - #address-cells = <1>;
  287. - #size-cells = <1>;
  288. - ranges;
  289. -
  290. - interrupt-parent = <&gic>;
  291. -
  292. - ehci: usb@21000 {
  293. - #usb-cells = <0>;
  294. -
  295. - compatible = "generic-ehci";
  296. - reg = <0x00021000 0x1000>;
  297. - interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
  298. - phys = <&usb2_phy>;
  299. -
  300. - #address-cells = <1>;
  301. - #size-cells = <0>;
  302. -
  303. - ehci_port1: port@1 {
  304. - reg = <1>;
  305. - #trigger-source-cells = <0>;
  306. - };
  307. -
  308. - ehci_port2: port@2 {
  309. - reg = <2>;
  310. - #trigger-source-cells = <0>;
  311. - };
  312. - };
  313. -
  314. - ohci: usb@22000 {
  315. - #usb-cells = <0>;
  316. -
  317. - compatible = "generic-ohci";
  318. - reg = <0x00022000 0x1000>;
  319. - interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
  320. -
  321. - #address-cells = <1>;
  322. - #size-cells = <0>;
  323. -
  324. - ohci_port1: port@1 {
  325. - reg = <1>;
  326. - #trigger-source-cells = <0>;
  327. - };
  328. -
  329. - ohci_port2: port@2 {
  330. - reg = <2>;
  331. - #trigger-source-cells = <0>;
  332. - };
  333. - };
  334. - };
  335. -
  336. - usb3: usb3@23000 {
  337. - reg = <0x00023000 0x1000>;
  338. -
  339. - #address-cells = <1>;
  340. - #size-cells = <1>;
  341. - ranges;
  342. -
  343. - interrupt-parent = <&gic>;
  344. -
  345. - xhci: usb@23000 {
  346. - #usb-cells = <0>;
  347. -
  348. - compatible = "generic-xhci";
  349. - reg = <0x00023000 0x1000>;
  350. - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
  351. - phys = <&usb3_phy>;
  352. - phy-names = "usb";
  353. -
  354. - #address-cells = <1>;
  355. - #size-cells = <0>;
  356. -
  357. - xhci_port1: port@1 {
  358. - reg = <1>;
  359. - #trigger-source-cells = <0>;
  360. - };
  361. - };
  362. - };
  363. -
  364. gmac0: ethernet@24000 {
  365. reg = <0x24000 0x800>;
  366. };
  367. @@ -355,13 +252,6 @@
  368. status = "disabled";
  369. };
  370. - mdio: mdio@18003000 {
  371. - compatible = "brcm,iproc-mdio";
  372. - reg = <0x18003000 0x8>;
  373. - #size-cells = <0>;
  374. - #address-cells = <1>;
  375. - };
  376. -
  377. mdio-mux@18003000 {
  378. compatible = "mdio-mux-mmioreg", "mdio-mux";
  379. mdio-parent-bus = <&mdio>;
  380. @@ -409,18 +299,7 @@
  381. };
  382. dmu-bus@1800c000 {
  383. - compatible = "simple-bus";
  384. - ranges = <0 0x1800c000 0x1000>;
  385. - #address-cells = <1>;
  386. - #size-cells = <1>;
  387. -
  388. cru-bus@100 {
  389. - compatible = "brcm,ns-cru", "simple-mfd";
  390. - reg = <0x100 0x1a4>;
  391. - ranges;
  392. - #address-cells = <1>;
  393. - #size-cells = <1>;
  394. -
  395. lcpll0: clock-controller@100 {
  396. #clock-cells = <1>;
  397. compatible = "brcm,nsp-lcpll0";
  398. @@ -440,53 +319,6 @@
  399. "usbclk", "iprocfast",
  400. "sata1", "sata2";
  401. };
  402. -
  403. - usb2_phy: phy@164 {
  404. - compatible = "brcm,ns-usb2-phy";
  405. - reg = <0x164 0x4>;
  406. - brcm,syscon-clkset = <&cru_clkset>;
  407. - clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
  408. - clock-names = "phy-ref-clk";
  409. - #phy-cells = <0>;
  410. - };
  411. -
  412. - cru_clkset: syscon@180 {
  413. - compatible = "brcm,cru-clkset", "syscon";
  414. - reg = <0x180 0x4>;
  415. - };
  416. -
  417. - pinctrl: pinctrl@1c0 {
  418. - compatible = "brcm,bcm4708-pinmux";
  419. - reg = <0x1c0 0x24>;
  420. - reg-names = "cru_gpio_control";
  421. -
  422. - spi-pins {
  423. - groups = "spi_grp";
  424. - function = "spi";
  425. - };
  426. -
  427. - pinmux_i2c: i2c-pins {
  428. - groups = "i2c_grp";
  429. - function = "i2c";
  430. - };
  431. -
  432. - pinmux_pwm: pwm-pins {
  433. - groups = "pwm0_grp", "pwm1_grp",
  434. - "pwm2_grp", "pwm3_grp";
  435. - function = "pwm";
  436. - };
  437. -
  438. - pinmux_uart1: uart1-pins {
  439. - groups = "uart1_grp";
  440. - function = "uart1";
  441. - };
  442. - };
  443. -
  444. - thermal: thermal@2c0 {
  445. - compatible = "brcm,ns-thermal";
  446. - reg = <0x2c0 0x10>;
  447. - #thermal-sensor-cells = <0>;
  448. - };
  449. };
  450. };
  451. @@ -557,24 +389,4 @@
  452. };
  453. };
  454. };
  455. -
  456. - thermal-zones {
  457. - cpu_thermal: cpu-thermal {
  458. - polling-delay-passive = <0>;
  459. - polling-delay = <1000>;
  460. - coefficients = <(-556) 418000>;
  461. - thermal-sensors = <&thermal>;
  462. -
  463. - trips {
  464. - cpu-crit {
  465. - temperature = <125000>;
  466. - hysteresis = <0>;
  467. - type = "critical";
  468. - };
  469. - };
  470. -
  471. - cooling-maps {
  472. - };
  473. - };
  474. - };
  475. };