| 12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455 |
- From b6a709cb51f7bdc55c01cec886098a9753ce8c28 Mon Sep 17 00:00:00 2001
- From: "Russell King (Oracle)" <[email protected]>
- Date: Thu, 27 Oct 2022 14:10:42 +0100
- Subject: [PATCH 01/10] net: mtk_eth_soc: add definitions for PCS
- As a result of help from Frank Wunderlich to investigate and test, we
- know a bit more about the PCS on the Mediatek platforms. Update the
- definitions from this investigation.
- This PCS appears similar, but not identical to the Lynx PCS.
- Although not included in this patch, but for future reference, the PHY
- ID registers at offset 4 read as 0x4d544950 'MTIP'.
- Signed-off-by: Russell King (Oracle) <[email protected]>
- Signed-off-by: Jakub Kicinski <[email protected]>
- ---
- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 13 ++++++++++---
- 1 file changed, 10 insertions(+), 3 deletions(-)
- --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
- +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
- @@ -501,8 +501,10 @@
- #define ETHSYS_DMA_AG_MAP_PPE BIT(2)
-
- /* SGMII subsystem config registers */
- -/* Register to auto-negotiation restart */
- +/* BMCR (low 16) BMSR (high 16) */
- #define SGMSYS_PCS_CONTROL_1 0x0
- +#define SGMII_BMCR GENMASK(15, 0)
- +#define SGMII_BMSR GENMASK(31, 16)
- #define SGMII_AN_RESTART BIT(9)
- #define SGMII_ISOLATE BIT(10)
- #define SGMII_AN_ENABLE BIT(12)
- @@ -512,13 +514,18 @@
- #define SGMII_PCS_FAULT BIT(23)
- #define SGMII_AN_EXPANSION_CLR BIT(30)
-
- +#define SGMSYS_PCS_ADVERTISE 0x8
- +#define SGMII_ADVERTISE GENMASK(15, 0)
- +#define SGMII_LPA GENMASK(31, 16)
- +
- /* Register to programmable link timer, the unit in 2 * 8ns */
- #define SGMSYS_PCS_LINK_TIMER 0x18
- -#define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0))
- +#define SGMII_LINK_TIMER_MASK GENMASK(19, 0)
- +#define SGMII_LINK_TIMER_DEFAULT (0x186a0 & SGMII_LINK_TIMER_MASK)
-
- /* Register to control remote fault */
- #define SGMSYS_SGMII_MODE 0x20
- -#define SGMII_IF_MODE_BIT0 BIT(0)
- +#define SGMII_IF_MODE_SGMII BIT(0)
- #define SGMII_SPEED_DUPLEX_AN BIT(1)
- #define SGMII_SPEED_MASK GENMASK(3, 2)
- #define SGMII_SPEED_10 FIELD_PREP(SGMII_SPEED_MASK, 0)
|
