724-net-mtk_sgmii-implement-mtk_pcs_ops.patch 1.5 KB

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  1. From cbfed00575d15eafd85efd9619b7ecc0836a4aa7 Mon Sep 17 00:00:00 2001
  2. From: Alexander Couzens <[email protected]>
  3. Date: Sat, 13 Aug 2022 14:42:12 +0200
  4. Subject: [PATCH 04/10] net: mtk_sgmii: implement mtk_pcs_ops
  5. Implement mtk_pcs_ops for the SGMII pcs to read the current state
  6. of the hardware.
  7. Signed-off-by: Alexander Couzens <[email protected]>
  8. [added DUPLEX_FULL]
  9. Signed-off-by: Daniel Golle <[email protected]>
  10. ---
  11. drivers/net/ethernet/mediatek/mtk_sgmii.c | 15 +++++++++++++++
  12. 1 file changed, 15 insertions(+)
  13. --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
  14. +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
  15. @@ -122,10 +122,28 @@ static void mtk_pcs_link_up(struct phyli
  16. regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
  17. }
  18. +static void mtk_pcs_get_state(struct phylink_pcs *pcs, struct phylink_link_state *state)
  19. +{
  20. + struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
  21. + unsigned int val;
  22. +
  23. + regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val);
  24. + state->an_complete = !!(val & SGMII_AN_COMPLETE);
  25. + state->link = !!(val & SGMII_LINK_STATYS);
  26. + if (!state->link)
  27. + return;
  28. +
  29. + regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val);
  30. + state->speed = val & RG_PHY_SPEED_3_125G ? SPEED_2500 : SPEED_1000;
  31. + state->duplex = DUPLEX_FULL;
  32. + state->pause = 0;
  33. +}
  34. +
  35. static const struct phylink_pcs_ops mtk_pcs_ops = {
  36. .pcs_config = mtk_pcs_config,
  37. .pcs_an_restart = mtk_pcs_restart_an,
  38. .pcs_link_up = mtk_pcs_link_up,
  39. + .pcs_get_state = mtk_pcs_get_state,
  40. };
  41. int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3)