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334-ath9k-use-REG_RMW-and-rmw-buffer-in-ath9k_hw_def_set.patch

334-ath9k-use-REG_RMW-and-rmw-buffer-in-ath9k_hw_def_set.patch 2.5 KB
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  1. From: Oleksij Rempel <[email protected]>
    2. 

  2. Date: Sun, 22 Mar 2015 19:30:03 +0100
    3. 

  3. Subject: [PATCH] ath9k: use REG_RMW and rmw buffer in
    4. 

  4.  ath9k_hw_def_set_gain
    5. 

  5. 

  6. Signed-off-by: Oleksij Rempel <[email protected]>
    7. 

  7. Signed-off-by: Kalle Valo <[email protected]>
    8. 

  8. ---
    9. 

  9. 

  10. --- a/drivers/net/wireless/ath/ath9k/eeprom_def.c
    11. 

  11. +++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
    12. 

  12. @@ -466,6 +466,7 @@ static void ath9k_hw_def_set_gain(struct
    13. 

  13.  				  struct ar5416_eeprom_def *eep,
    14. 

  14.  				  u8 txRxAttenLocal, int regChainOffset, int i)
    15. 

  15.  {
    16. 

  16. +	ENABLE_REG_RMW_BUFFER(ah);
    17. 

  17.  	if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
    18. 

  18.  		txRxAttenLocal = pModal->txRxAttenCh[i];
    19. 

  19.  
    20. 

  20. @@ -483,16 +484,12 @@ static void ath9k_hw_def_set_gain(struct
    21. 

  21.  			      AR_PHY_GAIN_2GHZ_XATTEN2_DB,
    22. 

  22.  			      pModal->xatten2Db[i]);
    23. 

  23.  		} else {
    24. 

  24. -			REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
    25. 

  25. -			  (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
    26. 

  26. -			   ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
    27. 

  27. -			  | SM(pModal-> bswMargin[i],
    28. 

  28. -			       AR_PHY_GAIN_2GHZ_BSW_MARGIN));
    29. 

  29. -			REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
    30. 

  30. -			  (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
    31. 

  31. -			   ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
    32. 

  32. -			  | SM(pModal->bswAtten[i],
    33. 

  33. -			       AR_PHY_GAIN_2GHZ_BSW_ATTEN));
    34. 

  34. +			REG_RMW(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
    35. 

  35. +				SM(pModal-> bswMargin[i], AR_PHY_GAIN_2GHZ_BSW_MARGIN),
    36. 

  36. +				AR_PHY_GAIN_2GHZ_BSW_MARGIN);
    37. 

  37. +			REG_RMW(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
    38. 

  38. +				SM(pModal->bswAtten[i], AR_PHY_GAIN_2GHZ_BSW_ATTEN),
    39. 

  39. +				AR_PHY_GAIN_2GHZ_BSW_ATTEN);
    40. 

  40.  		}
    41. 

  41.  	}
    42. 

  42.  
    43. 

  43. @@ -504,17 +501,14 @@ static void ath9k_hw_def_set_gain(struct
    44. 

  44.  		      AR_PHY_RXGAIN + regChainOffset,
    45. 

  45.  		      AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]);
    46. 

  46.  	} else {
    47. 

  47. -		REG_WRITE(ah,
    48. 

  48. -			  AR_PHY_RXGAIN + regChainOffset,
    49. 

  49. -			  (REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) &
    50. 

  50. -			   ~AR_PHY_RXGAIN_TXRX_ATTEN)
    51. 

  51. -			  | SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN));
    52. 

  52. -		REG_WRITE(ah,
    53. 

  53. -			  AR_PHY_GAIN_2GHZ + regChainOffset,
    54. 

  54. -			  (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
    55. 

  55. -			   ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
    56. 

  56. -			  SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
    57. 

  57. +		REG_RMW(ah, AR_PHY_RXGAIN + regChainOffset,
    58. 

  58. +			SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN),
    59. 

  59. +			AR_PHY_RXGAIN_TXRX_ATTEN);
    60. 

  60. +		REG_RMW(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
    61. 

  61. +			SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN),
    62. 

  62. +			AR_PHY_GAIN_2GHZ_RXTX_MARGIN);
    63. 

  63.  	}
    64. 

  64. +	REG_RMW_BUFFER_FLUSH(ah);
    65. 

  65.  }
    66. 

  66.  
    67. 

  67.  static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
    68.