0212-GPIO-ralink-add-mt7621-gpio-controller.patch 6.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244
  1. From 2a9b5a9fc1a0707b95dbe61dd1c30b9337cb457d Mon Sep 17 00:00:00 2001
  2. From: John Crispin <[email protected]>
  3. Date: Sun, 16 Mar 2014 05:26:34 +0000
  4. Subject: [PATCH 212/215] GPIO: ralink: add mt7621 gpio controller
  5. Signed-off-by: John Crispin <[email protected]>
  6. ---
  7. arch/mips/Kconfig | 5 +-
  8. drivers/gpio/Kconfig | 6 ++
  9. drivers/gpio/Makefile | 1 +
  10. drivers/gpio/gpio-mt7621.c | 183 ++++++++++++++++++++++++++++++++++++++++++++
  11. 4 files changed, 194 insertions(+), 1 deletion(-)
  12. create mode 100644 drivers/gpio/gpio-mt7621.c
  13. Index: linux-3.10.32/arch/mips/Kconfig
  14. ===================================================================
  15. --- linux-3.10.32.orig/arch/mips/Kconfig 2014-03-18 11:00:30.945639822 +0000
  16. +++ linux-3.10.32/arch/mips/Kconfig 2014-03-18 11:00:31.325639806 +0000
  17. @@ -448,7 +448,10 @@
  18. select ARCH_REQUIRE_GPIOLIB
  19. select PINCTRL
  20. select PINCTRL_RT2880
  21. -
  22. + select ARCH_HAS_RESET_CONTROLLER
  23. + select RESET_CONTROLLER
  24. + select ARCH_REQUIRE_GPIOLIB
  25. +
  26. config SGI_IP22
  27. bool "SGI IP22 (Indy/Indigo2)"
  28. select FW_ARC
  29. Index: linux-3.10.32/drivers/gpio/Kconfig
  30. ===================================================================
  31. --- linux-3.10.32.orig/drivers/gpio/Kconfig 2014-03-18 11:00:30.653639834 +0000
  32. +++ linux-3.10.32/drivers/gpio/Kconfig 2014-03-18 11:02:01.901636126 +0000
  33. @@ -710,6 +710,12 @@
  34. Enable support for GPIO on intel MSIC controllers found in
  35. intel MID devices
  36. +config GPIO_MT7621
  37. + bool "Mediatek GPIO Support"
  38. + depends on SOC_MT7621
  39. + help
  40. + Say yes here to support the Mediatek SoC GPIO device
  41. +
  42. comment "USB GPIO expanders:"
  43. config GPIO_VIPERBOARD
  44. Index: linux-3.10.32/drivers/gpio/Makefile
  45. ===================================================================
  46. --- linux-3.10.32.orig/drivers/gpio/Makefile 2014-03-18 11:00:30.653639834 +0000
  47. +++ linux-3.10.32/drivers/gpio/Makefile 2014-03-18 11:00:31.325639806 +0000
  48. @@ -88,3 +88,4 @@
  49. obj-$(CONFIG_GPIO_WM8350) += gpio-wm8350.o
  50. obj-$(CONFIG_GPIO_WM8994) += gpio-wm8994.o
  51. obj-$(CONFIG_GPIO_XILINX) += gpio-xilinx.o
  52. +obj-$(CONFIG_GPIO_MT7621) += gpio-mt7621.o
  53. Index: linux-3.10.32/drivers/gpio/gpio-mt7621.c
  54. ===================================================================
  55. --- /dev/null 1970-01-01 00:00:00.000000000 +0000
  56. +++ linux-3.10.32/drivers/gpio/gpio-mt7621.c 2014-03-18 11:00:31.325639806 +0000
  57. @@ -0,0 +1,183 @@
  58. +/*
  59. + * This program is free software; you can redistribute it and/or modify it
  60. + * under the terms of the GNU General Public License version 2 as published
  61. + * by the Free Software Foundation.
  62. + *
  63. + * Copyright (C) 2009-2011 Gabor Juhos <[email protected]>
  64. + * Copyright (C) 2013 John Crispin <[email protected]>
  65. + */
  66. +
  67. +#include <linux/io.h>
  68. +#include <linux/err.h>
  69. +#include <linux/gpio.h>
  70. +#include <linux/module.h>
  71. +#include <linux/of_irq.h>
  72. +#include <linux/spinlock.h>
  73. +#include <linux/irqdomain.h>
  74. +#include <linux/interrupt.h>
  75. +#include <linux/platform_device.h>
  76. +
  77. +#define MTK_BANK_WIDTH 32
  78. +
  79. +enum mediatek_gpio_reg {
  80. + GPIO_REG_CTRL = 0,
  81. + GPIO_REG_POL,
  82. + GPIO_REG_DATA,
  83. + GPIO_REG_DSET,
  84. + GPIO_REG_DCLR,
  85. +};
  86. +
  87. +static void __iomem *mtk_gc_membase;
  88. +
  89. +struct mtk_gc {
  90. + struct gpio_chip chip;
  91. + spinlock_t lock;
  92. + int bank;
  93. +};
  94. +
  95. +int
  96. +gpio_to_irq(unsigned gpio)
  97. +{
  98. + return -1;
  99. +}
  100. +
  101. +static inline struct mtk_gc
  102. +*to_mediatek_gpio(struct gpio_chip *chip)
  103. +{
  104. + struct mtk_gc *mgc;
  105. +
  106. + mgc = container_of(chip, struct mtk_gc, chip);
  107. +
  108. + return mgc;
  109. +}
  110. +
  111. +static inline void
  112. +mtk_gpio_w32(struct mtk_gc *rg, u8 reg, u32 val)
  113. +{
  114. + iowrite32(val, mtk_gc_membase + (reg * 0x10) + (rg->bank * 0x4));
  115. +}
  116. +
  117. +static inline u32
  118. +mtk_gpio_r32(struct mtk_gc *rg, u8 reg)
  119. +{
  120. + return ioread32(mtk_gc_membase + (reg * 0x10) + (rg->bank * 0x4));
  121. +}
  122. +
  123. +static void
  124. +mediatek_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  125. +{
  126. + struct mtk_gc *rg = to_mediatek_gpio(chip);
  127. +
  128. + mtk_gpio_w32(rg, (value) ? GPIO_REG_DSET : GPIO_REG_DCLR, BIT(offset));
  129. +}
  130. +
  131. +static int
  132. +mediatek_gpio_get(struct gpio_chip *chip, unsigned offset)
  133. +{
  134. + struct mtk_gc *rg = to_mediatek_gpio(chip);
  135. +
  136. + return !!(mtk_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
  137. +}
  138. +
  139. +static int
  140. +mediatek_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  141. +{
  142. + struct mtk_gc *rg = to_mediatek_gpio(chip);
  143. + unsigned long flags;
  144. + u32 t;
  145. +
  146. + spin_lock_irqsave(&rg->lock, flags);
  147. + t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
  148. + t &= ~BIT(offset);
  149. + mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
  150. + spin_unlock_irqrestore(&rg->lock, flags);
  151. +
  152. + return 0;
  153. +}
  154. +
  155. +static int
  156. +mediatek_gpio_direction_output(struct gpio_chip *chip,
  157. + unsigned offset, int value)
  158. +{
  159. + struct mtk_gc *rg = to_mediatek_gpio(chip);
  160. + unsigned long flags;
  161. + u32 t;
  162. +
  163. + spin_lock_irqsave(&rg->lock, flags);
  164. + t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
  165. + t |= BIT(offset);
  166. + mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
  167. + mediatek_gpio_set(chip, offset, value);
  168. + spin_unlock_irqrestore(&rg->lock, flags);
  169. +
  170. + return 0;
  171. +}
  172. +
  173. +static int
  174. +mediatek_gpio_bank_probe(struct platform_device *pdev, struct device_node *bank)
  175. +{
  176. + const __be32 *id = of_get_property(bank, "reg", NULL);
  177. + struct mtk_gc *rg = devm_kzalloc(&pdev->dev,
  178. + sizeof(struct mtk_gc), GFP_KERNEL);
  179. + if (!rg || !id)
  180. + return -ENOMEM;
  181. +
  182. + spin_lock_init(&rg->lock);
  183. +
  184. + rg->chip.dev = &pdev->dev;
  185. + rg->chip.label = dev_name(&pdev->dev);
  186. + rg->chip.of_node = bank;
  187. + rg->chip.base = MTK_BANK_WIDTH * be32_to_cpu(*id);
  188. + rg->chip.ngpio = MTK_BANK_WIDTH;
  189. + rg->chip.direction_input = mediatek_gpio_direction_input;
  190. + rg->chip.direction_output = mediatek_gpio_direction_output;
  191. + rg->chip.get = mediatek_gpio_get;
  192. + rg->chip.set = mediatek_gpio_set;
  193. +
  194. + /* set polarity to low for all gpios */
  195. + mtk_gpio_w32(rg, GPIO_REG_POL, 0);
  196. +
  197. + dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
  198. +
  199. + return gpiochip_add(&rg->chip);
  200. +}
  201. +
  202. +static int
  203. +mediatek_gpio_probe(struct platform_device *pdev)
  204. +{
  205. + struct device_node *bank, *np = pdev->dev.of_node;
  206. + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  207. +
  208. + mtk_gc_membase = devm_request_and_ioremap(&pdev->dev, res);
  209. + if (IS_ERR(mtk_gc_membase))
  210. + return PTR_ERR(mtk_gc_membase);
  211. +
  212. + for_each_child_of_node(np, bank)
  213. + if (of_device_is_compatible(bank, "mtk,mt7621-gpio-bank"))
  214. + mediatek_gpio_bank_probe(pdev, bank);
  215. +
  216. + return 0;
  217. +}
  218. +
  219. +static const struct of_device_id mediatek_gpio_match[] = {
  220. + { .compatible = "mtk,mt7621-gpio" },
  221. + {},
  222. +};
  223. +MODULE_DEVICE_TABLE(of, mediatek_gpio_match);
  224. +
  225. +static struct platform_driver mediatek_gpio_driver = {
  226. + .probe = mediatek_gpio_probe,
  227. + .driver = {
  228. + .name = "mt7621_gpio",
  229. + .owner = THIS_MODULE,
  230. + .of_match_table = mediatek_gpio_match,
  231. + },
  232. +};
  233. +
  234. +static int __init
  235. +mediatek_gpio_init(void)
  236. +{
  237. + return platform_driver_register(&mediatek_gpio_driver);
  238. +}
  239. +
  240. +subsys_initcall(mediatek_gpio_init);