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- From 55c14526f970805a6bf2ed4b820f062334375abe Mon Sep 17 00:00:00 2001
- From: Eugen Hristev <[email protected]>
- Date: Thu, 19 Nov 2020 17:43:09 +0200
- Subject: [PATCH 103/247] clk: at91: sama7g5: allow SYS and CPU PLLs to be
- exported and referenced in DT
- Allow SYSPLL and CPUPLL to be referenced as a PMC_TYPE_CORE clock
- from phandle in DT.
- Suggested-by: Claudiu Beznea <[email protected]>
- Signed-off-by: Eugen Hristev <[email protected]>
- [[email protected]: adapt commit message, add CPU PLL]
- Signed-off-by: Claudiu Beznea <[email protected]>
- Link: https://lore.kernel.org/r/[email protected]
- Signed-off-by: Stephen Boyd <[email protected]>
- ---
- drivers/clk/at91/sama7g5.c | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
- --- a/drivers/clk/at91/sama7g5.c
- +++ b/drivers/clk/at91/sama7g5.c
- @@ -117,7 +117,8 @@ static const struct {
- .p = "cpupll_fracck",
- .l = &pll_layout_divpmc,
- .t = PLL_TYPE_DIV,
- - .c = 1, },
- + .c = 1,
- + .eid = PMC_CPUPLL, },
- },
-
- [PLL_ID_SYS] = {
- @@ -131,7 +132,8 @@ static const struct {
- .p = "syspll_fracck",
- .l = &pll_layout_divpmc,
- .t = PLL_TYPE_DIV,
- - .c = 1, },
- + .c = 1,
- + .eid = PMC_SYSPLL, },
- },
-
- [PLL_ID_DDR] = {
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