111-clk-at91-sama7g5-register-cpu-clock.patch 2.4 KB

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  1. From 36e97c421dd9f866e31fe14bcb7af01334791890 Mon Sep 17 00:00:00 2001
  2. From: Claudiu Beznea <[email protected]>
  3. Date: Thu, 19 Nov 2020 17:43:17 +0200
  4. Subject: [PATCH 111/247] clk: at91: sama7g5: register cpu clock
  5. Register CPU clock as being the master clock prescaler. This would
  6. be used by DVFS. The block schema of SAMA7G5's PMC contains also a divider
  7. between master clock prescaler and CPU (PMC_CPU_RATIO.RATIO) but the
  8. frequencies supported by SAMA7G5 could be directly received from
  9. CPUPLL + master clock prescaler and the extra divider would do no work in
  10. case it would be enabled.
  11. Signed-off-by: Claudiu Beznea <[email protected]>
  12. Link: https://lore.kernel.org/r/[email protected]
  13. Signed-off-by: Stephen Boyd <[email protected]>
  14. ---
  15. drivers/clk/at91/sama7g5.c | 13 ++++++-------
  16. include/dt-bindings/clock/at91.h | 1 +
  17. 2 files changed, 7 insertions(+), 7 deletions(-)
  18. --- a/drivers/clk/at91/sama7g5.c
  19. +++ b/drivers/clk/at91/sama7g5.c
  20. @@ -904,7 +904,7 @@ static void __init sama7g5_pmc_setup(str
  21. if (IS_ERR(regmap))
  22. return;
  23. - sama7g5_pmc = pmc_data_allocate(PMC_ETHPLL + 1,
  24. + sama7g5_pmc = pmc_data_allocate(PMC_CPU + 1,
  25. nck(sama7g5_systemck),
  26. nck(sama7g5_periphck),
  27. nck(sama7g5_gck), 8);
  28. @@ -981,18 +981,17 @@ static void __init sama7g5_pmc_setup(str
  29. }
  30. }
  31. - parent_names[0] = md_slck_name;
  32. - parent_names[1] = "mainck";
  33. - parent_names[2] = "cpupll_divpmcck";
  34. - parent_names[3] = "syspll_divpmcck";
  35. - hw = at91_clk_register_master_pres(regmap, "mck0_pres", 4, parent_names,
  36. + parent_names[0] = "cpupll_divpmcck";
  37. + hw = at91_clk_register_master_pres(regmap, "cpuck", 1, parent_names,
  38. &mck0_layout, &mck0_characteristics,
  39. &pmc_mck0_lock,
  40. CLK_SET_RATE_PARENT, 0);
  41. if (IS_ERR(hw))
  42. goto err_free;
  43. - hw = at91_clk_register_master_div(regmap, "mck0_div", "mck0_pres",
  44. + sama7g5_pmc->chws[PMC_CPU] = hw;
  45. +
  46. + hw = at91_clk_register_master_div(regmap, "mck0", "cpuck",
  47. &mck0_layout, &mck0_characteristics,
  48. &pmc_mck0_lock, 0);
  49. if (IS_ERR(hw))
  50. --- a/include/dt-bindings/clock/at91.h
  51. +++ b/include/dt-bindings/clock/at91.h
  52. @@ -34,6 +34,7 @@
  53. #define PMC_AUDIOPMCPLL (PMC_MAIN + 6)
  54. #define PMC_AUDIOIOPLL (PMC_MAIN + 7)
  55. #define PMC_ETHPLL (PMC_MAIN + 8)
  56. +#define PMC_CPU (PMC_MAIN + 9)
  57. #ifndef AT91_PMC_MOSCS
  58. #define AT91_PMC_MOSCS 0 /* MOSCS Flag */