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- From 1b15259551b701f416aa024050a2e619860bd0d8 Mon Sep 17 00:00:00 2001
- From: Claudiu Beznea <[email protected]>
- Date: Wed, 9 Dec 2020 15:03:33 +0200
- Subject: [PATCH 116/247] net: macb: add capability to not set the clock rate
- SAMA7G5's ethernet IPs TX clock could be provided by its generic clock or
- by the external clock provided by the PHY. The internal IP logic divides
- properly this clock depending on the link speed. The patch adds a new
- capability so that macb_set_tx_clock() to not be called for IPs having
- this capability (the clock rate, in case of generic clock, is set at the
- boot time via device tree and the driver only enables it).
- Signed-off-by: Claudiu Beznea <[email protected]>
- Reviewed-by: Andrew Lunn <[email protected]>
- Signed-off-by: David S. Miller <[email protected]>
- ---
- drivers/net/ethernet/cadence/macb.h | 1 +
- drivers/net/ethernet/cadence/macb_main.c | 18 +++++++++---------
- 2 files changed, 10 insertions(+), 9 deletions(-)
- --- a/drivers/net/ethernet/cadence/macb.h
- +++ b/drivers/net/ethernet/cadence/macb.h
- @@ -658,6 +658,7 @@
- #define MACB_CAPS_GEM_HAS_PTP 0x00000040
- #define MACB_CAPS_BD_RD_PREFETCH 0x00000080
- #define MACB_CAPS_NEEDS_RSTONUBR 0x00000100
- +#define MACB_CAPS_CLK_HW_CHG 0x04000000
- #define MACB_CAPS_MACB_IS_EMAC 0x08000000
- #define MACB_CAPS_FIFO_MODE 0x10000000
- #define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000
- --- a/drivers/net/ethernet/cadence/macb_main.c
- +++ b/drivers/net/ethernet/cadence/macb_main.c
- @@ -457,15 +457,14 @@ static void macb_init_buffers(struct mac
-
- /**
- * macb_set_tx_clk() - Set a clock to a new frequency
- - * @clk: Pointer to the clock to change
- + * @bp: pointer to struct macb
- * @speed: New frequency in Hz
- - * @dev: Pointer to the struct net_device
- */
- -static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
- +static void macb_set_tx_clk(struct macb *bp, int speed)
- {
- long ferr, rate, rate_rounded;
-
- - if (!clk)
- + if (!bp->tx_clk || !(bp->caps & MACB_CAPS_CLK_HW_CHG))
- return;
-
- switch (speed) {
- @@ -482,7 +481,7 @@ static void macb_set_tx_clk(struct clk *
- return;
- }
-
- - rate_rounded = clk_round_rate(clk, rate);
- + rate_rounded = clk_round_rate(bp->tx_clk, rate);
- if (rate_rounded < 0)
- return;
-
- @@ -492,11 +491,12 @@ static void macb_set_tx_clk(struct clk *
- ferr = abs(rate_rounded - rate);
- ferr = DIV_ROUND_UP(ferr, rate / 100000);
- if (ferr > 5)
- - netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
- + netdev_warn(bp->dev,
- + "unable to generate target frequency: %ld Hz\n",
- rate);
-
- - if (clk_set_rate(clk, rate_rounded))
- - netdev_err(dev, "adjusting tx_clk failed.\n");
- + if (clk_set_rate(bp->tx_clk, rate_rounded))
- + netdev_err(bp->dev, "adjusting tx_clk failed.\n");
- }
-
- static void macb_validate(struct phylink_config *config,
- @@ -649,7 +649,7 @@ static void macb_mac_link_up(struct phyl
- if (rx_pause)
- ctrl |= MACB_BIT(PAE);
-
- - macb_set_tx_clk(bp->tx_clk, speed, ndev);
- + macb_set_tx_clk(bp, speed);
-
- /* Initialize rings & buffers as clearing MACB_BIT(TE) in link down
- * cleared the pipeline and control registers.
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