153-ASoC-mchp-i2s-mcc-Add-FIFOs-support.patch 6.4 KB

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  1. From 36bb4f0ab8e7ef69cc11d4d888aa898223b0e901 Mon Sep 17 00:00:00 2001
  2. From: Codrin Ciubotariu <[email protected]>
  3. Date: Mon, 1 Mar 2021 19:09:04 +0200
  4. Subject: [PATCH 153/247] ASoC: mchp-i2s-mcc: Add FIFOs support
  5. I2S-MCC found on SAMA7G5 includes 2 FIFOs (capture and playback). When
  6. FIFOs are enabled, bits I2SMCC_ISRA.TXLRDYx and I2SMCC_ISRA.TXRRDYx must
  7. not be used. Bits I2SMCC_ISRB.TXFFRDY and I2SMCC_ISRB.RXFFRDY must be used
  8. instead.
  9. Signed-off-by: Codrin Ciubotariu <[email protected]>
  10. Link: https://lore.kernel.org/r/[email protected]
  11. Signed-off-by: Mark Brown <[email protected]>
  12. ---
  13. sound/soc/atmel/mchp-i2s-mcc.c | 76 +++++++++++++++++++++++++---------
  14. 1 file changed, 56 insertions(+), 20 deletions(-)
  15. --- a/sound/soc/atmel/mchp-i2s-mcc.c
  16. +++ b/sound/soc/atmel/mchp-i2s-mcc.c
  17. @@ -176,7 +176,7 @@
  18. */
  19. #define MCHP_I2SMCC_MRB_CRAMODE_REGULAR (1 << 0)
  20. -#define MCHP_I2SMCC_MRB_FIFOEN BIT(1)
  21. +#define MCHP_I2SMCC_MRB_FIFOEN BIT(4)
  22. #define MCHP_I2SMCC_MRB_DMACHUNK_MASK GENMASK(9, 8)
  23. #define MCHP_I2SMCC_MRB_DMACHUNK(no_words) \
  24. @@ -230,6 +230,7 @@ static const struct regmap_config mchp_i
  25. struct mchp_i2s_mcc_soc_data {
  26. unsigned int data_pin_pair_num;
  27. + bool has_fifo;
  28. };
  29. struct mchp_i2s_mcc_dev {
  30. @@ -257,7 +258,7 @@ struct mchp_i2s_mcc_dev {
  31. static irqreturn_t mchp_i2s_mcc_interrupt(int irq, void *dev_id)
  32. {
  33. struct mchp_i2s_mcc_dev *dev = dev_id;
  34. - u32 sra, imra, srb, imrb, pendinga, pendingb, idra = 0;
  35. + u32 sra, imra, srb, imrb, pendinga, pendingb, idra = 0, idrb = 0;
  36. irqreturn_t ret = IRQ_NONE;
  37. regmap_read(dev->regmap, MCHP_I2SMCC_IMRA, &imra);
  38. @@ -275,24 +276,36 @@ static irqreturn_t mchp_i2s_mcc_interrup
  39. * Tx/Rx ready interrupts are enabled when stopping only, to assure
  40. * availability and to disable clocks if necessary
  41. */
  42. - idra |= pendinga & (MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels) |
  43. - MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels));
  44. - if (idra)
  45. + if (dev->soc->has_fifo) {
  46. + idrb |= pendingb & (MCHP_I2SMCC_INT_TXFFRDY |
  47. + MCHP_I2SMCC_INT_RXFFRDY);
  48. + } else {
  49. + idra |= pendinga & (MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels) |
  50. + MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels));
  51. + }
  52. + if (idra || idrb)
  53. ret = IRQ_HANDLED;
  54. - if ((imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) &&
  55. - (imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) ==
  56. - (idra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels))) {
  57. + if ((!dev->soc->has_fifo &&
  58. + (imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) &&
  59. + (imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) ==
  60. + (idra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels))) ||
  61. + (dev->soc->has_fifo && imrb & MCHP_I2SMCC_INT_TXFFRDY)) {
  62. dev->tx_rdy = 1;
  63. wake_up_interruptible(&dev->wq_txrdy);
  64. }
  65. - if ((imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) &&
  66. - (imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) ==
  67. - (idra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels))) {
  68. + if ((!dev->soc->has_fifo &&
  69. + (imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) &&
  70. + (imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) ==
  71. + (idra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels))) ||
  72. + (dev->soc->has_fifo && imrb & MCHP_I2SMCC_INT_RXFFRDY)) {
  73. dev->rx_rdy = 1;
  74. wake_up_interruptible(&dev->wq_rxrdy);
  75. }
  76. - regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, idra);
  77. + if (dev->soc->has_fifo)
  78. + regmap_write(dev->regmap, MCHP_I2SMCC_IDRB, idrb);
  79. + else
  80. + regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, idra);
  81. return ret;
  82. }
  83. @@ -664,6 +677,10 @@ static int mchp_i2s_mcc_hw_params(struct
  84. }
  85. }
  86. + /* enable FIFO if available */
  87. + if (dev->soc->has_fifo)
  88. + mrb |= MCHP_I2SMCC_MRB_FIFOEN;
  89. +
  90. /*
  91. * If we are already running, the wanted setup must be
  92. * the same with the one that's currently ongoing
  93. @@ -726,8 +743,13 @@ static int mchp_i2s_mcc_hw_free(struct s
  94. if (err == 0) {
  95. dev_warn_once(dev->dev,
  96. "Timeout waiting for Tx ready\n");
  97. - regmap_write(dev->regmap, MCHP_I2SMCC_IDRA,
  98. - MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels));
  99. + if (dev->soc->has_fifo)
  100. + regmap_write(dev->regmap, MCHP_I2SMCC_IDRB,
  101. + MCHP_I2SMCC_INT_TXFFRDY);
  102. + else
  103. + regmap_write(dev->regmap, MCHP_I2SMCC_IDRA,
  104. + MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels));
  105. +
  106. dev->tx_rdy = 1;
  107. }
  108. } else {
  109. @@ -737,8 +759,12 @@ static int mchp_i2s_mcc_hw_free(struct s
  110. if (err == 0) {
  111. dev_warn_once(dev->dev,
  112. "Timeout waiting for Rx ready\n");
  113. - regmap_write(dev->regmap, MCHP_I2SMCC_IDRA,
  114. - MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels));
  115. + if (dev->soc->has_fifo)
  116. + regmap_write(dev->regmap, MCHP_I2SMCC_IDRB,
  117. + MCHP_I2SMCC_INT_RXFFRDY);
  118. + else
  119. + regmap_write(dev->regmap, MCHP_I2SMCC_IDRA,
  120. + MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels));
  121. dev->rx_rdy = 1;
  122. }
  123. }
  124. @@ -765,7 +791,7 @@ static int mchp_i2s_mcc_trigger(struct s
  125. struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
  126. bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
  127. u32 cr = 0;
  128. - u32 iera = 0;
  129. + u32 iera = 0, ierb = 0;
  130. u32 sr;
  131. int err;
  132. @@ -789,7 +815,10 @@ static int mchp_i2s_mcc_trigger(struct s
  133. * Enable Tx Ready interrupts on all channels
  134. * to assure all data is sent
  135. */
  136. - iera = MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels);
  137. + if (dev->soc->has_fifo)
  138. + ierb = MCHP_I2SMCC_INT_TXFFRDY;
  139. + else
  140. + iera = MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels);
  141. } else if (!is_playback && (sr & MCHP_I2SMCC_SR_RXEN)) {
  142. cr = MCHP_I2SMCC_CR_RXDIS;
  143. dev->rx_rdy = 0;
  144. @@ -797,7 +826,10 @@ static int mchp_i2s_mcc_trigger(struct s
  145. * Enable Rx Ready interrupts on all channels
  146. * to assure all data is received
  147. */
  148. - iera = MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels);
  149. + if (dev->soc->has_fifo)
  150. + ierb = MCHP_I2SMCC_INT_RXFFRDY;
  151. + else
  152. + iera = MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels);
  153. }
  154. break;
  155. default:
  156. @@ -815,7 +847,10 @@ static int mchp_i2s_mcc_trigger(struct s
  157. }
  158. }
  159. - regmap_write(dev->regmap, MCHP_I2SMCC_IERA, iera);
  160. + if (dev->soc->has_fifo)
  161. + regmap_write(dev->regmap, MCHP_I2SMCC_IERB, ierb);
  162. + else
  163. + regmap_write(dev->regmap, MCHP_I2SMCC_IERA, iera);
  164. regmap_write(dev->regmap, MCHP_I2SMCC_CR, cr);
  165. return 0;
  166. @@ -903,6 +938,7 @@ static struct mchp_i2s_mcc_soc_data mchp
  167. static struct mchp_i2s_mcc_soc_data mchp_i2s_mcc_sama7g5 = {
  168. .data_pin_pair_num = 4,
  169. + .has_fifo = true,
  170. };
  171. static const struct of_device_id mchp_i2s_mcc_dt_ids[] = {