soc_rt3050.c 4.3 KB

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  1. /* This program is free software; you can redistribute it and/or modify
  2. * it under the terms of the GNU General Public License as published by
  3. * the Free Software Foundation; version 2 of the License
  4. *
  5. * This program is distributed in the hope that it will be useful,
  6. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  7. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  8. * GNU General Public License for more details.
  9. *
  10. * Copyright (C) 2009-2015 John Crispin <[email protected]>
  11. * Copyright (C) 2009-2015 Felix Fietkau <[email protected]>
  12. * Copyright (C) 2013-2015 Michael Lee <[email protected]>
  13. */
  14. #include <linux/module.h>
  15. #include <asm/mach-ralink/ralink_regs.h>
  16. #include "mtk_eth_soc.h"
  17. #include "mdio_rt2880.h"
  18. #define RT305X_RESET_FE BIT(21)
  19. #define RT305X_RESET_ESW BIT(23)
  20. static const u16 rt5350_reg_table[FE_REG_COUNT] = {
  21. [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
  22. [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
  23. [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
  24. [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
  25. [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
  26. [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
  27. [FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
  28. [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
  29. [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
  30. [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
  31. [FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
  32. [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
  33. [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
  34. [FE_REG_FE_RST_GL] = 0,
  35. [FE_REG_FE_DMA_VID_BASE] = 0,
  36. };
  37. static void rt305x_init_data(struct fe_soc_data *data,
  38. struct net_device *netdev)
  39. {
  40. struct fe_priv *priv = netdev_priv(netdev);
  41. priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG |
  42. FE_FLAG_CALIBRATE_CLK | FE_FLAG_HAS_SWITCH;
  43. netdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
  44. NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX;
  45. }
  46. static int rt3050_fwd_config(struct fe_priv *priv)
  47. {
  48. int ret;
  49. if (ralink_soc != RT305X_SOC_RT3052) {
  50. ret = fe_set_clock_cycle(priv);
  51. if (ret)
  52. return ret;
  53. }
  54. fe_fwd_config(priv);
  55. if (ralink_soc != RT305X_SOC_RT3352)
  56. fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
  57. fe_csum_config(priv);
  58. return 0;
  59. }
  60. static void rt305x_fe_reset(void)
  61. {
  62. fe_reset(RT305X_RESET_FE);
  63. }
  64. static void rt5350_init_data(struct fe_soc_data *data,
  65. struct net_device *netdev)
  66. {
  67. struct fe_priv *priv = netdev_priv(netdev);
  68. priv->flags = FE_FLAG_HAS_SWITCH;
  69. netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM;
  70. }
  71. static void rt5350_set_mac(struct fe_priv *priv, unsigned char *mac)
  72. {
  73. unsigned long flags;
  74. spin_lock_irqsave(&priv->page_lock, flags);
  75. fe_w32((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH);
  76. fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
  77. RT5350_SDM_MAC_ADRL);
  78. spin_unlock_irqrestore(&priv->page_lock, flags);
  79. }
  80. static void rt5350_rxcsum_config(bool enable)
  81. {
  82. if (enable)
  83. fe_w32(fe_r32(RT5350_SDM_CFG) | (RT5350_SDM_ICS_EN |
  84. RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN),
  85. RT5350_SDM_CFG);
  86. else
  87. fe_w32(fe_r32(RT5350_SDM_CFG) & ~(RT5350_SDM_ICS_EN |
  88. RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN),
  89. RT5350_SDM_CFG);
  90. }
  91. static int rt5350_fwd_config(struct fe_priv *priv)
  92. {
  93. struct net_device *dev = priv_netdev(priv);
  94. rt5350_rxcsum_config((dev->features & NETIF_F_RXCSUM));
  95. return 0;
  96. }
  97. static void rt5350_tx_dma(struct fe_tx_dma *txd)
  98. {
  99. txd->txd4 = 0;
  100. }
  101. static void rt5350_fe_reset(void)
  102. {
  103. fe_reset(RT305X_RESET_FE | RT305X_RESET_ESW);
  104. }
  105. static struct fe_soc_data rt3050_data = {
  106. .init_data = rt305x_init_data,
  107. .reset_fe = rt305x_fe_reset,
  108. .fwd_config = rt3050_fwd_config,
  109. .pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
  110. .checksum_bit = RX_DMA_L4VALID,
  111. .rx_int = FE_RX_DONE_INT,
  112. .tx_int = FE_TX_DONE_INT,
  113. .status_int = FE_CNT_GDM_AF,
  114. };
  115. static struct fe_soc_data rt5350_data = {
  116. .init_data = rt5350_init_data,
  117. .reg_table = rt5350_reg_table,
  118. .reset_fe = rt5350_fe_reset,
  119. .set_mac = rt5350_set_mac,
  120. .fwd_config = rt5350_fwd_config,
  121. .tx_dma = rt5350_tx_dma,
  122. .pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
  123. .checksum_bit = RX_DMA_L4VALID,
  124. .rx_int = RT5350_RX_DONE_INT,
  125. .tx_int = RT5350_TX_DONE_INT,
  126. };
  127. const struct of_device_id of_fe_match[] = {
  128. { .compatible = "ralink,rt3050-eth", .data = &rt3050_data },
  129. { .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
  130. {},
  131. };
  132. MODULE_DEVICE_TABLE(of, of_fe_match);