0024-arm64-allwinner-a64-add-r_ccu-node.patch 1.5 KB

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  1. From 791a9e001d3ba3b552888b0bf3c592a50b71f57e Mon Sep 17 00:00:00 2001
  2. From: Icenowy Zheng <[email protected]>
  3. Date: Tue, 4 Apr 2017 17:50:58 +0800
  4. Subject: arm64: allwinner: a64: add r_ccu node
  5. A64 SoC have a CCU (r_ccu) in PRCM block.
  6. Add the device node for it.
  7. The mux 3 of R_CCU is an internal oscillator, which is 16MHz according
  8. to the user manual, and has only 30% accuracy based on our experience
  9. on older SoCs. The real mesaured value of it on two Pine64 boards is
  10. around 11MHz, which is around 70% of 16MHz.
  11. Signed-off-by: Icenowy Zheng <[email protected]>
  12. Signed-off-by: Maxime Ripard <[email protected]>
  13. ---
  14. arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 17 +++++++++++++++++
  15. 1 file changed, 17 insertions(+)
  16. --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
  17. +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
  18. @@ -98,6 +98,14 @@
  19. clock-output-names = "osc32k";
  20. };
  21. + iosc: internal-osc-clk {
  22. + #clock-cells = <0>;
  23. + compatible = "fixed-clock";
  24. + clock-frequency = <16000000>;
  25. + clock-accuracy = <300000000>;
  26. + clock-output-names = "iosc";
  27. + };
  28. +
  29. psci {
  30. compatible = "arm,psci-0.2";
  31. method = "smc";
  32. @@ -389,5 +397,14 @@
  33. interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
  34. <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
  35. };
  36. +
  37. + r_ccu: clock@1f01400 {
  38. + compatible = "allwinner,sun50i-a64-r-ccu";
  39. + reg = <0x01f01400 0x100>;
  40. + clocks = <&osc24M>, <&osc32k>, <&iosc>;
  41. + clock-names = "hosc", "losc", "iosc";
  42. + #clock-cells = <1>;
  43. + #reset-cells = <1>;
  44. + };
  45. };
  46. };