qcom-ipq8062-wg2600hp3.dts 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. #include "qcom-ipq8062.dtsi"
  3. #include <dt-bindings/input/input.h>
  4. /delete-node/ &nand_pins;
  5. / {
  6. model = "NEC Platforms Aterm WG2600HP3";
  7. compatible = "nec,wg2600hp3", "qcom,ipq8062", "qcom,ipq8064";
  8. memory {
  9. device_type = "memory";
  10. reg = <0x42000000 0x1e000000>;
  11. };
  12. aliases {
  13. label-mac-device = &gmac2;
  14. led-boot = &led_power_green;
  15. led-failsafe = &led_power_red;
  16. led-running = &led_power_green;
  17. led-upgrade = &led_power_red;
  18. };
  19. keys {
  20. compatible = "gpio-keys";
  21. pinctrl-0 = <&buttons_pins>;
  22. pinctrl-names = "default";
  23. reset {
  24. label = "reset";
  25. gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>;
  26. linux,code = <KEY_RESTART>;
  27. };
  28. wps {
  29. label = "wps";
  30. gpios = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>;
  31. linux,code = <KEY_WPS_BUTTON>;
  32. };
  33. mode0 {
  34. label = "mode0";
  35. gpios = <&qcom_pinmux 40 GPIO_ACTIVE_LOW>;
  36. linux,code = <BTN_0>;
  37. linux,input-type = <EV_SW>;
  38. };
  39. mode1 {
  40. label = "mode1";
  41. gpios = <&qcom_pinmux 41 GPIO_ACTIVE_LOW>;
  42. linux,code = <BTN_1>;
  43. linux,input-type = <EV_SW>;
  44. };
  45. };
  46. leds {
  47. compatible = "gpio-leds";
  48. pinctrl-0 = <&leds_pins>;
  49. pinctrl-names = "default";
  50. led_power_green: power_green {
  51. label = "green:power";
  52. gpios = <&qcom_pinmux 14 GPIO_ACTIVE_HIGH>;
  53. };
  54. led_power_red: power_red {
  55. label = "red:power";
  56. gpios = <&qcom_pinmux 35 GPIO_ACTIVE_HIGH>;
  57. };
  58. active_green {
  59. label = "green:active";
  60. gpios = <&qcom_pinmux 42 GPIO_ACTIVE_HIGH>;
  61. };
  62. active_red {
  63. label = "red:active";
  64. gpios = <&qcom_pinmux 38 GPIO_ACTIVE_HIGH>;
  65. };
  66. wlan2g_green {
  67. label = "green:wlan2g";
  68. gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;
  69. linux,default-trigger = "phy1tpt";
  70. };
  71. wlan2g_red {
  72. label = "red:wlan2g";
  73. gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
  74. };
  75. wlan5g_green {
  76. label = "green:wlan5g";
  77. gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>;
  78. linux,default-trigger = "phy0tpt";
  79. };
  80. wlan5g_red {
  81. label = "red:wlan5g";
  82. gpios = <&qcom_pinmux 58 GPIO_ACTIVE_HIGH>;
  83. };
  84. tv_green {
  85. label = "green:tv";
  86. gpios = <&qcom_pinmux 46 GPIO_ACTIVE_HIGH>;
  87. };
  88. tv_red {
  89. label = "red:tv";
  90. gpios = <&qcom_pinmux 36 GPIO_ACTIVE_HIGH>;
  91. };
  92. converter_green {
  93. label = "green:converter";
  94. gpios = <&qcom_pinmux 43 GPIO_ACTIVE_HIGH>;
  95. };
  96. converter_red {
  97. label = "red:converter";
  98. gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>;
  99. };
  100. };
  101. };
  102. &qcom_pinmux {
  103. pinctrl-0 = <&akro_pins>;
  104. pinctrl-names = "default";
  105. spi_pins: spi_pins {
  106. mux {
  107. pins = "gpio18", "gpio19", "gpio21";
  108. function = "gsbi5";
  109. bias-pull-down;
  110. };
  111. data {
  112. pins = "gpio18", "gpio19";
  113. drive-strength = <10>;
  114. };
  115. cs {
  116. pins = "gpio20";
  117. drive-strength = <10>;
  118. };
  119. clk {
  120. pins = "gpio21";
  121. drive-strength = <12>;
  122. };
  123. };
  124. buttons_pins: buttons_pins {
  125. mux {
  126. pins = "gpio22", "gpio24", "gpio40",
  127. "gpio41";
  128. function = "gpio";
  129. drive-strength = <2>;
  130. bias-pull-up;
  131. };
  132. };
  133. leds_pins: leds_pins {
  134. mux {
  135. pins = "gpio14", "gpio15", "gpio35",
  136. "gpio36", "gpio38", "gpio42",
  137. "gpio43", "gpio46", "gpio55",
  138. "gpio56", "gpio57", "gpio58";
  139. function = "gpio";
  140. bias-pull-down;
  141. };
  142. akro2 {
  143. pins = "gpio15", "gpio35", "gpio38",
  144. "gpio42", "gpio43", "gpio46",
  145. "gpio55", "gpio56", "gpio57",
  146. "gpio58";
  147. drive-strength = <2>;
  148. };
  149. akro4 {
  150. pins = "gpio14", "gpio36";
  151. drive-strength = <4>;
  152. };
  153. };
  154. /*
  155. * Stock firmware has the following settings, so let's do the same.
  156. * I don't sure why these are required.
  157. */
  158. akro_pins: akro_pinmux {
  159. akro {
  160. pins = "gpio17", "gpio26", "gpio47";
  161. function = "gpio";
  162. drive-strength = <2>;
  163. bias-pull-down;
  164. };
  165. reset {
  166. pins = "gpio45";
  167. function = "gpio";
  168. drive-strength = <2>;
  169. bias-disable;
  170. output-low;
  171. };
  172. gmac0_rgmii {
  173. pins = "gpio25";
  174. function = "gpio";
  175. drive-strength = <8>;
  176. bias-disable;
  177. };
  178. };
  179. };
  180. &gsbi5 {
  181. status = "okay";
  182. qcom,mode = <GSBI_PROT_SPI>;
  183. spi@1a280000 {
  184. status = "okay";
  185. pinctrl-0 = <&spi_pins>;
  186. pinctrl-names = "default";
  187. cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
  188. flash@0 {
  189. compatible = "jedec,spi-nor";
  190. reg = <0>;
  191. spi-max-frequency = <50000000>;
  192. m25p,fast-read;
  193. partitions {
  194. compatible = "fixed-partitions";
  195. #address-cells = <1>;
  196. #size-cells = <1>;
  197. partition@0 {
  198. label = "SBL1";
  199. reg = <0x0000000 0x0020000>;
  200. read-only;
  201. };
  202. partition@20000 {
  203. label = "MIBIB";
  204. reg = <0x0020000 0x0020000>;
  205. read-only;
  206. };
  207. partition@40000 {
  208. label = "SBL2";
  209. reg = <0x0040000 0x0040000>;
  210. read-only;
  211. };
  212. partition@80000 {
  213. label = "SBL3";
  214. reg = <0x0080000 0x0080000>;
  215. read-only;
  216. };
  217. partition@100000 {
  218. label = "DDRCONFIG";
  219. reg = <0x0100000 0x0010000>;
  220. read-only;
  221. };
  222. partition@110000 {
  223. label = "SSD";
  224. reg = <0x0110000 0x0010000>;
  225. read-only;
  226. };
  227. partition@120000 {
  228. label = "TZ";
  229. reg = <0x0120000 0x0080000>;
  230. read-only;
  231. };
  232. partition@1a0000 {
  233. label = "RPM";
  234. reg = <0x01a0000 0x0080000>;
  235. read-only;
  236. };
  237. partition@220000 {
  238. label = "APPSBL";
  239. reg = <0x0220000 0x0080000>;
  240. read-only;
  241. };
  242. partition@2a0000 {
  243. label = "APPSBLENV";
  244. reg = <0x02a0000 0x0010000>;
  245. read-only;
  246. };
  247. factory: partition@2b0000 {
  248. label = "PRODUCTDATA";
  249. reg = <0x02b0000 0x0030000>;
  250. read-only;
  251. };
  252. partition@2e0000 {
  253. label = "ART";
  254. reg = <0x02e0000 0x0040000>;
  255. read-only;
  256. };
  257. partition@320000 {
  258. label = "TP";
  259. reg = <0x0320000 0x0040000>;
  260. read-only;
  261. };
  262. partition@360000 {
  263. label = "TINY";
  264. reg = <0x0360000 0x0500000>;
  265. read-only;
  266. };
  267. partition@860000 {
  268. compatible = "denx,uimage";
  269. label = "firmware";
  270. reg = <0x0860000 0x17a0000>;
  271. };
  272. };
  273. };
  274. };
  275. };
  276. &adm_dma {
  277. status = "okay";
  278. };
  279. &pcie0 {
  280. status = "okay";
  281. bridge@0,0 {
  282. reg = <0x00000000 0 0 0 0>;
  283. #address-cells = <3>;
  284. #size-cells = <2>;
  285. ranges;
  286. wifi@1,0 {
  287. compatible = "qcom,ath10k";
  288. reg = <0x00010000 0 0 0 0>;
  289. qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3";
  290. };
  291. };
  292. };
  293. &pcie1 {
  294. status = "okay";
  295. force_gen1 = <1>;
  296. bridge@0,0 {
  297. reg = <0x00000000 0 0 0 0>;
  298. #address-cells = <3>;
  299. #size-cells = <2>;
  300. ranges;
  301. wifi@1,0 {
  302. compatible = "qcom,ath10k";
  303. reg = <0x00010000 0 0 0 0>;
  304. ieee80211-freq-limit = <2400000 2483000>;
  305. qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3";
  306. };
  307. };
  308. };
  309. &mdio0 {
  310. status = "okay";
  311. pinctrl-0 = <&mdio0_pins>;
  312. pinctrl-names = "default";
  313. phy0: ethernet-phy@0 {
  314. reg = <0>;
  315. qca,ar8327-initvals = <
  316. 0x04 0x80080080 /* PAD0_MODE */
  317. 0x0c 0x06000000 /* PAD6_MODE */
  318. 0x10 0x002613a0 /* PWS_REG */
  319. 0x50 0xcc36cc36 /* LED_CTRL0 */
  320. 0x54 0xca36ca36 /* LED_CTRL1 */
  321. 0x58 0xc936c936 /* LED_CTRL2 */
  322. 0x5c 0x03ffff00 /* LED_CTRL3 */
  323. 0x7c 0x0000004e /* PORT0_STATUS */
  324. 0x94 0x0000004e /* PORT6_STATUS */
  325. 0xe0 0xc74164de /* SGMII_CTRL */
  326. 0xe4 0x0006a545 /* MAC_PWR_SEL */
  327. >;
  328. };
  329. };
  330. &gmac1 {
  331. status = "okay";
  332. pinctrl-0 = <&rgmii2_pins>;
  333. pinctrl-names = "default";
  334. phy-mode = "rgmii";
  335. qcom,id = <1>;
  336. mdiobus = <&mdio0>;
  337. mtd-mac-address = <&factory 0x0>;
  338. fixed-link {
  339. speed = <1000>;
  340. full-duplex;
  341. };
  342. };
  343. &gmac2 {
  344. status = "okay";
  345. phy-mode = "sgmii";
  346. qcom,id = <2>;
  347. mdiobus = <&mdio0>;
  348. mtd-mac-address = <&factory 0x6>;
  349. fixed-link {
  350. speed = <1000>;
  351. full-duplex;
  352. };
  353. };