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- From bef5018abb7cf94efafdc05087b4c998891ae4ec Mon Sep 17 00:00:00 2001
- From: Ansuel Smith <[email protected]>
- Date: Mon, 17 Jan 2022 23:39:34 +0100
- Subject: [PATCH v3 10/18] ARM: dts: qcom: add saw for l2 cache and kraitcc for
- ipq8064
- Add saw compatible for l2 cache and kraitcc node for ipq8064 dtsi.
- Also declare clock-output-names for acc0 and acc1 and qsb fixed clock
- for the secondary mux.
- Signed-off-by: Ansuel Smith <[email protected]>
- Tested-by: Jonathan McDowell <[email protected]>
- ---
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 34 +++++++++++++++++++++++++++--
- 1 file changed, 32 insertions(+), 2 deletions(-)
- --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
- +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
- @@ -301,6 +301,12 @@
- };
-
- clocks {
- + qsb: qsb {
- + compatible = "fixed-clock";
- + clock-frequency = <225000000>;
- + #clock-cells = <0>;
- + };
- +
- cxo_board: cxo_board {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- @@ -575,15 +581,30 @@
- clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
- clock-names = "pll8_vote", "pxo";
- clock-output-names = "acpu_l2_aux";
- + #clock-cells = <0>;
- + };
- +
- + kraitcc: clock-controller {
- + compatible = "qcom,krait-cc-v1";
- + clocks = <&gcc PLL9>, <&gcc PLL10>, <&gcc PLL12>,
- + <&acc0>, <&acc1>, <&l2cc>, <&qsb>, <&pxo_board>;
- + clock-names = "hfpll0", "hfpll1", "hfpll_l2",
- + "acpu0_aux", "acpu1_aux", "acpu_l2_aux",
- + "qsb", "pxo";
- + #clock-cells = <1>;
- };
-
- acc0: clock-controller@2088000 {
- compatible = "qcom,kpss-acc-v1";
- reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
- + clock-output-names = "acpu0_aux";
- + clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
- + clock-names = "pll8_vote", "pxo";
- + #clock-cells = <0>;
- };
-
- saw0: regulator@2089000 {
- - compatible = "qcom,saw2";
- + compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
- reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
- regulator;
- };
- @@ -591,14 +612,24 @@
- acc1: clock-controller@2098000 {
- compatible = "qcom,kpss-acc-v1";
- reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
- + clock-output-names = "acpu1_aux";
- + clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
- + clock-names = "pll8_vote", "pxo";
- + #clock-cells = <0>;
- };
-
- saw1: regulator@2099000 {
- - compatible = "qcom,saw2";
- + compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
- reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
- regulator;
- };
-
- + saw_l2: regulator@02012000 {
- + compatible = "qcom,saw2", "syscon";
- + reg = <0x02012000 0x1000>;
- + regulator;
- + };
- +
- nss_common: syscon@03000000 {
- compatible = "syscon";
- reg = <0x03000000 0x0000FFFF>;
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