0030-riscv-dts-allwinner-Add-Sipeed-Lichee-RV-devicetrees.patch 8.3 KB

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  1. From 3bf76e93011425ed64a69c462b9959ed2a8ccf46 Mon Sep 17 00:00:00 2001
  2. From: Samuel Holland <[email protected]>
  3. Date: Wed, 29 Jun 2022 00:13:50 -0500
  4. Subject: [PATCH 030/117] riscv: dts: allwinner: Add Sipeed Lichee RV
  5. devicetrees
  6. Sipeed manufactures a "Lichee RV" system-on-module, which provides a
  7. minimal working system on its own, as well as a few carrier boards. The
  8. "Dock" board provides audio, USB, and WiFi. The "86 Panel" additionally
  9. provides 100M Ethernet and a built-in display panel.
  10. The 86 Panel repurposes the USB ID and VBUS detection GPIOs for its RGB
  11. panel interface, since the USB OTG port is inaccessible inside the case.
  12. Co-developed-by: Jisheng Zhang <[email protected]>
  13. Signed-off-by: Jisheng Zhang <[email protected]>
  14. Signed-off-by: Samuel Holland <[email protected]>
  15. ---
  16. arch/riscv/boot/dts/allwinner/Makefile | 4 +
  17. .../sun20i-d1-lichee-rv-86-panel-480p.dts | 29 ++++++
  18. .../sun20i-d1-lichee-rv-86-panel-720p.dts | 10 ++
  19. .../sun20i-d1-lichee-rv-86-panel.dtsi | 92 +++++++++++++++++++
  20. .../allwinner/sun20i-d1-lichee-rv-dock.dts | 74 +++++++++++++++
  21. .../dts/allwinner/sun20i-d1-lichee-rv.dts | 84 +++++++++++++++++
  22. 6 files changed, 293 insertions(+)
  23. create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
  24. create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts
  25. create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi
  26. create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
  27. create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
  28. --- a/arch/riscv/boot/dts/allwinner/Makefile
  29. +++ b/arch/riscv/boot/dts/allwinner/Makefile
  30. @@ -1,2 +1,6 @@
  31. # SPDX-License-Identifier: GPL-2.0
  32. +dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-480p.dtb
  33. +dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-720p.dtb
  34. +dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-dock.dtb
  35. +dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv.dtb
  36. dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb
  37. --- /dev/null
  38. +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
  39. @@ -0,0 +1,29 @@
  40. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  41. +// Copyright (C) 2022 Samuel Holland <[email protected]>
  42. +
  43. +#include "sun20i-d1-lichee-rv-86-panel.dtsi"
  44. +
  45. +/ {
  46. + model = "Sipeed Lichee RV 86 Panel (480p)";
  47. + compatible = "sipeed,lichee-rv-86-panel-480p", "sipeed,lichee-rv",
  48. + "allwinner,sun20i-d1";
  49. +};
  50. +
  51. +&i2c2 {
  52. + pinctrl-0 = <&i2c2_pb0_pins>;
  53. + pinctrl-names = "default";
  54. + status = "okay";
  55. +
  56. + touchscreen@48 {
  57. + compatible = "focaltech,ft6236";
  58. + reg = <0x48>;
  59. + interrupt-parent = <&pio>;
  60. + interrupts = <6 14 IRQ_TYPE_LEVEL_LOW>; /* PG14 */
  61. + iovcc-supply = <&reg_vcc_3v3>;
  62. + reset-gpios = <&pio 6 15 GPIO_ACTIVE_LOW>; /* PG15 */
  63. + touchscreen-size-x = <480>;
  64. + touchscreen-size-y = <480>;
  65. + vcc-supply = <&reg_vcc_3v3>;
  66. + wakeup-source;
  67. + };
  68. +};
  69. --- /dev/null
  70. +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts
  71. @@ -0,0 +1,10 @@
  72. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  73. +// Copyright (C) 2022 Samuel Holland <[email protected]>
  74. +
  75. +#include "sun20i-d1-lichee-rv-86-panel.dtsi"
  76. +
  77. +/ {
  78. + model = "Sipeed Lichee RV 86 Panel (720p)";
  79. + compatible = "sipeed,lichee-rv-86-panel-720p", "sipeed,lichee-rv",
  80. + "allwinner,sun20i-d1";
  81. +};
  82. --- /dev/null
  83. +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi
  84. @@ -0,0 +1,92 @@
  85. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  86. +// Copyright (C) 2022 Samuel Holland <[email protected]>
  87. +
  88. +#include "sun20i-d1-lichee-rv.dts"
  89. +
  90. +/ {
  91. + aliases {
  92. + ethernet0 = &emac;
  93. + ethernet1 = &xr829;
  94. + };
  95. +
  96. + /* PC1 is repurposed as BT_WAKE_AP */
  97. + /delete-node/ leds;
  98. +
  99. + wifi_pwrseq: wifi-pwrseq {
  100. + compatible = "mmc-pwrseq-simple";
  101. + clocks = <&ccu CLK_FANOUT1>;
  102. + clock-names = "ext_clock";
  103. + reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
  104. + assigned-clocks = <&ccu CLK_FANOUT1>;
  105. + assigned-clock-rates = <32768>;
  106. + pinctrl-0 = <&clk_pg11_pin>;
  107. + pinctrl-names = "default";
  108. + };
  109. +};
  110. +
  111. +&ehci1 {
  112. + status = "okay";
  113. +};
  114. +
  115. +&emac {
  116. + pinctrl-0 = <&rmii_pe_pins>;
  117. + pinctrl-names = "default";
  118. + phy-handle = <&ext_rmii_phy>;
  119. + phy-mode = "rmii";
  120. + phy-supply = <&reg_vcc_3v3>;
  121. + status = "okay";
  122. +};
  123. +
  124. +&mdio {
  125. + ext_rmii_phy: ethernet-phy@1 {
  126. + compatible = "ethernet-phy-ieee802.3-c22";
  127. + reg = <1>;
  128. + reset-gpios = <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */
  129. + };
  130. +};
  131. +
  132. +&mmc1 {
  133. + bus-width = <4>;
  134. + mmc-pwrseq = <&wifi_pwrseq>;
  135. + non-removable;
  136. + vmmc-supply = <&reg_vcc_3v3>;
  137. + vqmmc-supply = <&reg_vcc_3v3>;
  138. + pinctrl-0 = <&mmc1_pins>;
  139. + pinctrl-names = "default";
  140. + status = "okay";
  141. +
  142. + xr829: wifi@1 {
  143. + reg = <1>;
  144. + };
  145. +};
  146. +
  147. +&ohci1 {
  148. + status = "okay";
  149. +};
  150. +
  151. +&pio {
  152. + clk_pg11_pin: clk-pg11-pin {
  153. + pins = "PG11";
  154. + function = "clk";
  155. + };
  156. +};
  157. +
  158. +&uart1 {
  159. + uart-has-rtscts;
  160. + pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
  161. + pinctrl-names = "default";
  162. + status = "okay";
  163. +
  164. + /* XR829 bluetooth is connected here */
  165. +};
  166. +
  167. +&usb_otg {
  168. + status = "disabled";
  169. +};
  170. +
  171. +&usbphy {
  172. + /* PD20 and PD21 are repurposed for the LCD panel */
  173. + /delete-property/ usb0_id_det-gpios;
  174. + /delete-property/ usb0_vbus_det-gpios;
  175. + usb1_vbus-supply = <&reg_vcc>;
  176. +};
  177. --- /dev/null
  178. +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
  179. @@ -0,0 +1,74 @@
  180. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  181. +// Copyright (C) 2022 Jisheng Zhang <[email protected]>
  182. +// Copyright (C) 2022 Samuel Holland <[email protected]>
  183. +
  184. +#include <dt-bindings/input/input.h>
  185. +
  186. +#include "sun20i-d1-lichee-rv.dts"
  187. +
  188. +/ {
  189. + model = "Sipeed Lichee RV Dock";
  190. + compatible = "sipeed,lichee-rv-dock", "sipeed,lichee-rv",
  191. + "allwinner,sun20i-d1";
  192. +
  193. + aliases {
  194. + ethernet1 = &rtl8723ds;
  195. + };
  196. +
  197. + wifi_pwrseq: wifi-pwrseq {
  198. + compatible = "mmc-pwrseq-simple";
  199. + reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
  200. + };
  201. +};
  202. +
  203. +&ehci1 {
  204. + status = "okay";
  205. +};
  206. +
  207. +&lradc {
  208. + status = "okay";
  209. +
  210. + button-220 {
  211. + label = "OK";
  212. + linux,code = <KEY_OK>;
  213. + channel = <0>;
  214. + voltage = <220000>;
  215. + };
  216. +};
  217. +
  218. +&mmc1 {
  219. + bus-width = <4>;
  220. + mmc-pwrseq = <&wifi_pwrseq>;
  221. + non-removable;
  222. + vmmc-supply = <&reg_vcc_3v3>;
  223. + vqmmc-supply = <&reg_vcc_3v3>;
  224. + pinctrl-0 = <&mmc1_pins>;
  225. + pinctrl-names = "default";
  226. + status = "okay";
  227. +
  228. + rtl8723ds: wifi@1 {
  229. + reg = <1>;
  230. + };
  231. +};
  232. +
  233. +&ohci1 {
  234. + status = "okay";
  235. +};
  236. +
  237. +&uart1 {
  238. + uart-has-rtscts;
  239. + pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
  240. + pinctrl-names = "default";
  241. + status = "okay";
  242. +
  243. + bluetooth {
  244. + compatible = "realtek,rtl8723ds-bt";
  245. + device-wake-gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG16 */
  246. + enable-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 */
  247. + host-wake-gpios = <&pio 6 17 GPIO_ACTIVE_HIGH>; /* PG17 */
  248. + };
  249. +};
  250. +
  251. +&usbphy {
  252. + usb1_vbus-supply = <&reg_vcc>;
  253. +};
  254. --- /dev/null
  255. +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
  256. @@ -0,0 +1,84 @@
  257. +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
  258. +// Copyright (C) 2022 Jisheng Zhang <[email protected]>
  259. +// Copyright (C) 2022 Samuel Holland <[email protected]>
  260. +
  261. +/dts-v1/;
  262. +
  263. +#include <dt-bindings/gpio/gpio.h>
  264. +#include <dt-bindings/leds/common.h>
  265. +
  266. +#include "sun20i-d1.dtsi"
  267. +#include "sun20i-d1-common-regulators.dtsi"
  268. +
  269. +/ {
  270. + model = "Sipeed Lichee RV";
  271. + compatible = "sipeed,lichee-rv", "allwinner,sun20i-d1";
  272. +
  273. + aliases {
  274. + mmc0 = &mmc0;
  275. + serial0 = &uart0;
  276. + };
  277. +
  278. + chosen {
  279. + stdout-path = "serial0:115200n8";
  280. + };
  281. +
  282. + leds {
  283. + compatible = "gpio-leds";
  284. +
  285. + led-0 {
  286. + color = <LED_COLOR_ID_GREEN>;
  287. + function = LED_FUNCTION_STATUS;
  288. + gpios = <&pio 2 1 GPIO_ACTIVE_HIGH>; /* PC1 */
  289. + };
  290. + };
  291. +
  292. + reg_vdd_cpu: vdd-cpu {
  293. + compatible = "regulator-fixed";
  294. + regulator-name = "vdd-cpu";
  295. + regulator-min-microvolt = <900000>;
  296. + regulator-max-microvolt = <900000>;
  297. + vin-supply = <&reg_vcc>;
  298. + };
  299. +};
  300. +
  301. +&cpu0 {
  302. + cpu-supply = <&reg_vdd_cpu>;
  303. +};
  304. +
  305. +&ehci0 {
  306. + status = "okay";
  307. +};
  308. +
  309. +&mmc0 {
  310. + broken-cd;
  311. + bus-width = <4>;
  312. + disable-wp;
  313. + vmmc-supply = <&reg_vcc_3v3>;
  314. + vqmmc-supply = <&reg_vcc_3v3>;
  315. + pinctrl-0 = <&mmc0_pins>;
  316. + pinctrl-names = "default";
  317. + status = "okay";
  318. +};
  319. +
  320. +&ohci0 {
  321. + status = "okay";
  322. +};
  323. +
  324. +&uart0 {
  325. + pinctrl-0 = <&uart0_pb8_pins>;
  326. + pinctrl-names = "default";
  327. + status = "okay";
  328. +};
  329. +
  330. +&usb_otg {
  331. + dr_mode = "otg";
  332. + status = "okay";
  333. +};
  334. +
  335. +&usbphy {
  336. + usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
  337. + usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
  338. + usb0_vbus-supply = <&reg_vcc>;
  339. + status = "okay";
  340. +};