0077-spi-spi-sun6i-Dual-Quad-RX-Support.patch 1.7 KB

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  1. From b300b013de16109f833782d9f4e7ee8cc204780f Mon Sep 17 00:00:00 2001
  2. From: Samuel Holland <[email protected]>
  3. Date: Sat, 17 Jul 2021 11:19:29 -0500
  4. Subject: [PATCH 077/117] spi: spi-sun6i: Dual/Quad RX Support
  5. Signed-off-by: Samuel Holland <[email protected]>
  6. ---
  7. drivers/spi/spi-sun6i.c | 17 +++++++++++++++--
  8. 1 file changed, 15 insertions(+), 2 deletions(-)
  9. --- a/drivers/spi/spi-sun6i.c
  10. +++ b/drivers/spi/spi-sun6i.c
  11. @@ -82,6 +82,8 @@
  12. #define SUN6I_XMIT_CNT_REG 0x34
  13. #define SUN6I_BURST_CTL_CNT_REG 0x38
  14. +#define SUN6I_BURST_CTL_CNT_QUAD_EN BIT(29)
  15. +#define SUN6I_BURST_CTL_CNT_DUAL_EN BIT(28)
  16. #define SUN6I_TXDATA_REG 0x200
  17. #define SUN6I_RXDATA_REG 0x300
  18. @@ -415,7 +417,17 @@ static int sun6i_spi_transfer_one(struct
  19. /* Setup the counters */
  20. sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len);
  21. sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, tx_len);
  22. - sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, tx_len);
  23. +
  24. + reg = tx_len;
  25. + switch (tfr->rx_nbits) {
  26. + case SPI_NBITS_QUAD:
  27. + reg |= SUN6I_BURST_CTL_CNT_QUAD_EN;
  28. + break;
  29. + case SPI_NBITS_DUAL:
  30. + reg |= SUN6I_BURST_CTL_CNT_DUAL_EN;
  31. + break;
  32. + }
  33. + sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, reg);
  34. if (!use_dma) {
  35. /* Fill the TX FIFO */
  36. @@ -632,7 +644,8 @@ static int sun6i_spi_probe(struct platfo
  37. master->set_cs = sun6i_spi_set_cs;
  38. master->transfer_one = sun6i_spi_transfer_one;
  39. master->num_chipselect = 4;
  40. - master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
  41. + master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST
  42. + | SPI_RX_DUAL | SPI_RX_QUAD;
  43. master->bits_per_word_mask = SPI_BPW_MASK(8);
  44. master->dev.of_node = pdev->dev.of_node;
  45. master->auto_runtime_pm = true;