0090-riscv-dts-allwinner-d1-Add-DSI-pipeline.patch 2.1 KB

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  1. From 4c72279c90469971ca5ec627a76e50bf51bf076f Mon Sep 17 00:00:00 2001
  2. From: Samuel Holland <[email protected]>
  3. Date: Sun, 7 Aug 2022 10:59:29 -0500
  4. Subject: [PATCH 090/117] riscv: dts: allwinner: d1: Add DSI pipeline
  5. Signed-off-by: Samuel Holland <[email protected]>
  6. ---
  7. arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 49 ++++++++++++++++++++
  8. 1 file changed, 49 insertions(+)
  9. --- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
  10. +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
  11. @@ -124,6 +124,14 @@
  12. #interrupt-cells = <3>;
  13. /omit-if-no-ref/
  14. + dsi_4lane_pins: dsi-4lane-pins {
  15. + pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
  16. + "PD6", "PD7", "PD8", "PD9";
  17. + drive-strength = <30>;
  18. + function = "dsi";
  19. + };
  20. +
  21. + /omit-if-no-ref/
  22. i2c0_pb10_pins: i2c0-pb10-pins {
  23. pins = "PB10", "PB11";
  24. function = "i2c0";
  25. @@ -903,6 +911,40 @@
  26. };
  27. };
  28. + dsi: dsi@5450000 {
  29. + compatible = "allwinner,sun20i-d1-mipi-dsi",
  30. + "allwinner,sun50i-a100-mipi-dsi";
  31. + reg = <0x5450000 0x1000>;
  32. + interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
  33. + clocks = <&ccu CLK_BUS_MIPI_DSI>,
  34. + <&tcon_top CLK_TCON_TOP_DSI>;
  35. + clock-names = "bus", "mod";
  36. + resets = <&ccu RST_BUS_MIPI_DSI>;
  37. + phys = <&dphy>;
  38. + phy-names = "dphy";
  39. + status = "disabled";
  40. + #address-cells = <1>;
  41. + #size-cells = <0>;
  42. +
  43. + port {
  44. + dsi_in_tcon_lcd0: endpoint {
  45. + remote-endpoint = <&tcon_lcd0_out_dsi>;
  46. + };
  47. + };
  48. + };
  49. +
  50. + dphy: phy@5451000 {
  51. + compatible = "allwinner,sun20i-d1-mipi-dphy",
  52. + "allwinner,sun50i-a100-mipi-dphy";
  53. + reg = <0x5451000 0x1000>;
  54. + interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
  55. + clocks = <&ccu CLK_BUS_MIPI_DSI>,
  56. + <&ccu CLK_MIPI_DSI>;
  57. + clock-names = "bus", "mod";
  58. + resets = <&ccu RST_BUS_MIPI_DSI>;
  59. + #phy-cells = <0>;
  60. + };
  61. +
  62. tcon_top: tcon-top@5460000 {
  63. compatible = "allwinner,sun20i-d1-tcon-top";
  64. reg = <0x5460000 0x1000>;
  65. @@ -1022,6 +1064,13 @@
  66. tcon_lcd0_out: port@1 {
  67. reg = <1>;
  68. + #address-cells = <1>;
  69. + #size-cells = <0>;
  70. +
  71. + tcon_lcd0_out_dsi: endpoint@1 {
  72. + reg = <1>;
  73. + remote-endpoint = <&dsi_in_tcon_lcd0>;
  74. + };
  75. };
  76. };
  77. };