033-v6.0-0005-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM6856.patchgit 4.1 KB

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  1. From 64eca7ad058cff861b48cdead8dee40dfc284e9e Mon Sep 17 00:00:00 2001
  2. From: William Zhang <[email protected]>
  3. Date: Wed, 8 Jun 2022 11:04:36 -0700
  4. Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM6856
  5. Add DTS for ARMv8 based broadband SoC BCM6856. bcm6856.dtsi is the
  6. SoC description DTS header and bcm96856.dts is a simple DTS file for
  7. Broadcom BCM96956 Reference board that only enable the UART port.
  8. Signed-off-by: William Zhang <[email protected]>
  9. Signed-off-by: Florian Fainelli <[email protected]>
  10. ---
  11. arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +-
  12. .../boot/dts/broadcom/bcmbca/bcm6856.dtsi | 103 ++++++++++++++++++
  13. .../boot/dts/broadcom/bcmbca/bcm96856.dts | 30 +++++
  14. 3 files changed, 135 insertions(+), 1 deletion(-)
  15. create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
  16. create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
  17. --- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
  18. +++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
  19. @@ -8,4 +8,5 @@ dtb-$(CONFIG_ARCH_BCMBCA) += \
  20. bcm94912.dtb \
  21. bcm963158.dtb \
  22. bcm96858.dtb \
  23. - bcm963146.dtb
  24. + bcm963146.dtb \
  25. + bcm96856.dtb
  26. --- /dev/null
  27. +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
  28. @@ -0,0 +1,103 @@
  29. +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  30. +/*
  31. + * Copyright 2022 Broadcom Ltd.
  32. + */
  33. +
  34. +#include <dt-bindings/interrupt-controller/irq.h>
  35. +#include <dt-bindings/interrupt-controller/arm-gic.h>
  36. +
  37. +/ {
  38. + compatible = "brcm,bcm6856", "brcm,bcmbca";
  39. + #address-cells = <2>;
  40. + #size-cells = <2>;
  41. +
  42. + interrupt-parent = <&gic>;
  43. +
  44. + cpus {
  45. + #address-cells = <2>;
  46. + #size-cells = <0>;
  47. +
  48. + B53_0: cpu@0 {
  49. + compatible = "brcm,brahma-b53";
  50. + device_type = "cpu";
  51. + reg = <0x0 0x0>;
  52. + next-level-cache = <&L2_0>;
  53. + enable-method = "psci";
  54. + };
  55. +
  56. + B53_1: cpu@1 {
  57. + compatible = "brcm,brahma-b53";
  58. + device_type = "cpu";
  59. + reg = <0x0 0x1>;
  60. + next-level-cache = <&L2_0>;
  61. + enable-method = "psci";
  62. + };
  63. +
  64. + L2_0: l2-cache0 {
  65. + compatible = "cache";
  66. + };
  67. + };
  68. +
  69. + timer {
  70. + compatible = "arm,armv8-timer";
  71. + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  72. + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  73. + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  74. + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  75. + };
  76. +
  77. + pmu: pmu {
  78. + compatible = "arm,cortex-a53-pmu";
  79. + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
  80. + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
  81. + interrupt-affinity = <&B53_0>, <&B53_1>;
  82. + };
  83. +
  84. + clocks: clocks {
  85. + periph_clk:periph-clk {
  86. + compatible = "fixed-clock";
  87. + #clock-cells = <0>;
  88. + clock-frequency = <200000000>;
  89. + };
  90. + };
  91. +
  92. + psci {
  93. + compatible = "arm,psci-0.2";
  94. + method = "smc";
  95. + };
  96. +
  97. + axi@81000000 {
  98. + compatible = "simple-bus";
  99. + #address-cells = <1>;
  100. + #size-cells = <1>;
  101. + ranges = <0x0 0x0 0x81000000 0x8000>;
  102. +
  103. + gic: interrupt-controller@1000 {
  104. + compatible = "arm,gic-400";
  105. + #interrupt-cells = <3>;
  106. + interrupt-controller;
  107. + reg = <0x1000 0x1000>, /* GICD */
  108. + <0x2000 0x2000>, /* GICC */
  109. + <0x4000 0x2000>, /* GICH */
  110. + <0x6000 0x2000>; /* GICV */
  111. + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
  112. + IRQ_TYPE_LEVEL_HIGH)>;
  113. + };
  114. + };
  115. +
  116. + bus@ff800000 {
  117. + compatible = "simple-bus";
  118. + #address-cells = <1>;
  119. + #size-cells = <1>;
  120. + ranges = <0x0 0x0 0xff800000 0x800000>;
  121. +
  122. + uart0: serial@640 {
  123. + compatible = "brcm,bcm6345-uart";
  124. + reg = <0x640 0x18>;
  125. + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  126. + clocks = <&periph_clk>;
  127. + clock-names = "refclk";
  128. + status = "disabled";
  129. + };
  130. + };
  131. +};
  132. --- /dev/null
  133. +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
  134. @@ -0,0 +1,30 @@
  135. +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  136. +/*
  137. + * Copyright 2022 Broadcom Ltd.
  138. + */
  139. +
  140. +/dts-v1/;
  141. +
  142. +#include "bcm6856.dtsi"
  143. +
  144. +/ {
  145. + model = "Broadcom BCM96856 Reference Board";
  146. + compatible = "brcm,bcm96856", "brcm,bcm6856", "brcm,bcmbca";
  147. +
  148. + aliases {
  149. + serial0 = &uart0;
  150. + };
  151. +
  152. + chosen {
  153. + stdout-path = "serial0:115200n8";
  154. + };
  155. +
  156. + memory@0 {
  157. + device_type = "memory";
  158. + reg = <0x0 0x0 0x0 0x08000000>;
  159. + };
  160. +};
  161. +
  162. +&uart0 {
  163. + status = "okay";
  164. +};