789-STABLE-01-net-dsa-mt7530-prevent-possible-incorrect-XTAL-frequ.patch 6.2 KB

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  1. From be4512b9ac6fc53e1ca8daccbda84f643215c547 Mon Sep 17 00:00:00 2001
  2. From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <[email protected]>
  3. Date: Thu, 14 Mar 2024 12:28:35 +0300
  4. Subject: [PATCH 1/3] net: dsa: mt7530: prevent possible incorrect XTAL
  5. frequency selection
  6. MIME-Version: 1.0
  7. Content-Type: text/plain; charset=UTF-8
  8. Content-Transfer-Encoding: 8bit
  9. [ Upstream commit f490c492e946d8ffbe65ad4efc66de3c5ede30a4 ]
  10. On MT7530, the HT_XTAL_FSEL field of the HWTRAP register stores a 2-bit
  11. value that represents the frequency of the crystal oscillator connected to
  12. the switch IC. The field is populated by the state of the ESW_P4_LED_0 and
  13. ESW_P4_LED_0 pins, which is done right after reset is deasserted.
  14. ESW_P4_LED_0 ESW_P3_LED_0 Frequency
  15. -----------------------------------------
  16. 0 0 Reserved
  17. 0 1 20MHz
  18. 1 0 40MHz
  19. 1 1 25MHz
  20. On MT7531, the XTAL25 bit of the STRAP register stores this. The LAN0LED0
  21. pin is used to populate the bit. 25MHz when the pin is high, 40MHz when
  22. it's low.
  23. These pins are also used with LEDs, therefore, their state can be set to
  24. something other than the bootstrapping configuration. For example, a link
  25. may be established on port 3 before the DSA subdriver takes control of the
  26. switch which would set ESW_P3_LED_0 to high.
  27. Currently on mt7530_setup() and mt7531_setup(), 1000 - 1100 usec delay is
  28. described between reset assertion and deassertion. Some switch ICs in real
  29. life conditions cannot always have these pins set back to the bootstrapping
  30. configuration before reset deassertion in this amount of delay. This causes
  31. wrong crystal frequency to be selected which puts the switch in a
  32. nonfunctional state after reset deassertion.
  33. The tests below are conducted on an MT7530 with a 40MHz crystal oscillator
  34. by Justin Swartz.
  35. With a cable from an active peer connected to port 3 before reset, an
  36. incorrect crystal frequency (0b11 = 25MHz) is selected:
  37. [1] [3] [5]
  38. : : :
  39. _____________________________ __________________
  40. ESW_P4_LED_0 |_______|
  41. _____________________________
  42. ESW_P3_LED_0 |__________________________
  43. : : : :
  44. : : [4]...:
  45. : :
  46. [2]................:
  47. [1] Reset is asserted.
  48. [2] Period of 1000 - 1100 usec.
  49. [3] Reset is deasserted.
  50. [4] Period of 315 usec. HWTRAP register is populated with incorrect
  51. XTAL frequency.
  52. [5] Signals reflect the bootstrapped configuration.
  53. Increase the delay between reset_control_assert() and
  54. reset_control_deassert(), and gpiod_set_value_cansleep(priv->reset, 0) and
  55. gpiod_set_value_cansleep(priv->reset, 1) to 5000 - 5100 usec. This amount
  56. ensures a higher possibility that the switch IC will have these pins back
  57. to the bootstrapping configuration before reset deassertion.
  58. With a cable from an active peer connected to port 3 before reset, the
  59. correct crystal frequency (0b10 = 40MHz) is selected:
  60. [1] [2-1] [3] [5]
  61. : : : :
  62. _____________________________ __________________
  63. ESW_P4_LED_0 |_______|
  64. ___________________ _______
  65. ESW_P3_LED_0 |_________| |__________________
  66. : : : : :
  67. : [2-2]...: [4]...:
  68. [2]................:
  69. [1] Reset is asserted.
  70. [2] Period of 5000 - 5100 usec.
  71. [2-1] ESW_P3_LED_0 goes low.
  72. [2-2] Remaining period of 5000 - 5100 usec.
  73. [3] Reset is deasserted.
  74. [4] Period of 310 usec. HWTRAP register is populated with bootstrapped
  75. XTAL frequency.
  76. [5] Signals reflect the bootstrapped configuration.
  77. ESW_P3_LED_0 low period before reset deassertion:
  78. 5000 usec
  79. - 5100 usec
  80. TEST RESET HOLD
  81. # (usec)
  82. ---------------------
  83. 1 5410
  84. 2 5440
  85. 3 4375
  86. 4 5490
  87. 5 5475
  88. 6 4335
  89. 7 4370
  90. 8 5435
  91. 9 4205
  92. 10 4335
  93. 11 3750
  94. 12 3170
  95. 13 4395
  96. 14 4375
  97. 15 3515
  98. 16 4335
  99. 17 4220
  100. 18 4175
  101. 19 4175
  102. 20 4350
  103. Min 3170
  104. Max 5490
  105. Median 4342.500
  106. Avg 4466.500
  107. Revert commit 2920dd92b980 ("net: dsa: mt7530: disable LEDs before reset").
  108. Changing the state of pins via reset assertion is simpler and more
  109. efficient than doing so by setting the LED controller off.
  110. Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch")
  111. Fixes: c288575f7810 ("net: dsa: mt7530: Add the support of MT7531 switch")
  112. Co-developed-by: Justin Swartz <[email protected]>
  113. Signed-off-by: Justin Swartz <[email protected]>
  114. Signed-off-by: Arınç ÜNAL <[email protected]>
  115. Signed-off-by: David S. Miller <[email protected]>
  116. Signed-off-by: Sasha Levin <[email protected]>
  117. ---
  118. drivers/net/dsa/mt7530.c | 8 ++++----
  119. 1 file changed, 4 insertions(+), 4 deletions(-)
  120. --- a/drivers/net/dsa/mt7530.c
  121. +++ b/drivers/net/dsa/mt7530.c
  122. @@ -2187,11 +2187,11 @@ mt7530_setup(struct dsa_switch *ds)
  123. */
  124. if (priv->mcm) {
  125. reset_control_assert(priv->rstc);
  126. - usleep_range(1000, 1100);
  127. + usleep_range(5000, 5100);
  128. reset_control_deassert(priv->rstc);
  129. } else {
  130. gpiod_set_value_cansleep(priv->reset, 0);
  131. - usleep_range(1000, 1100);
  132. + usleep_range(5000, 5100);
  133. gpiod_set_value_cansleep(priv->reset, 1);
  134. }
  135. @@ -2401,11 +2401,11 @@ mt7531_setup(struct dsa_switch *ds)
  136. */
  137. if (priv->mcm) {
  138. reset_control_assert(priv->rstc);
  139. - usleep_range(1000, 1100);
  140. + usleep_range(5000, 5100);
  141. reset_control_deassert(priv->rstc);
  142. } else {
  143. gpiod_set_value_cansleep(priv->reset, 0);
  144. - usleep_range(1000, 1100);
  145. + usleep_range(5000, 5100);
  146. gpiod_set_value_cansleep(priv->reset, 1);
  147. }