790-14-v6.4-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch 12 KB

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  1. From a1b87b6322db9186c8689710fe3e98f59e540949 Mon Sep 17 00:00:00 2001
  2. From: Daniel Golle <[email protected]>
  3. Date: Mon, 3 Apr 2023 02:19:40 +0100
  4. Subject: [PATCH 14/48] net: dsa: mt7530: introduce driver for MT7988 built-in
  5. switch
  6. Add driver for the built-in Gigabit Ethernet switch which can be found
  7. in the MediaTek MT7988 SoC.
  8. The switch shares most of its design with MT7530 and MT7531, but has
  9. it's registers mapped into the SoCs register space rather than being
  10. connected externally or internally via MDIO.
  11. Introduce a new platform driver to support that.
  12. Signed-off-by: Daniel Golle <[email protected]>
  13. Reviewed-by: Andrew Lunn <[email protected]>
  14. Signed-off-by: David S. Miller <[email protected]>
  15. ---
  16. MAINTAINERS | 2 +
  17. drivers/net/dsa/Kconfig | 12 +++
  18. drivers/net/dsa/Makefile | 1 +
  19. drivers/net/dsa/mt7530-mmio.c | 101 +++++++++++++++++++++++++
  20. drivers/net/dsa/mt7530.c | 135 +++++++++++++++++++++++++++++++++-
  21. drivers/net/dsa/mt7530.h | 12 +--
  22. 6 files changed, 253 insertions(+), 10 deletions(-)
  23. create mode 100644 drivers/net/dsa/mt7530-mmio.c
  24. --- a/MAINTAINERS
  25. +++ b/MAINTAINERS
  26. @@ -13067,9 +13067,11 @@ MEDIATEK SWITCH DRIVER
  27. M: Sean Wang <[email protected]>
  28. M: Landen Chao <[email protected]>
  29. M: DENG Qingfang <[email protected]>
  30. +M: Daniel Golle <[email protected]>
  31. L: [email protected]
  32. S: Maintained
  33. F: drivers/net/dsa/mt7530-mdio.c
  34. +F: drivers/net/dsa/mt7530-mmio.c
  35. F: drivers/net/dsa/mt7530.*
  36. F: net/dsa/tag_mtk.c
  37. --- a/drivers/net/dsa/Kconfig
  38. +++ b/drivers/net/dsa/Kconfig
  39. @@ -37,6 +37,7 @@ config NET_DSA_MT7530
  40. tristate "MediaTek MT7530 and MT7531 Ethernet switch support"
  41. select NET_DSA_TAG_MTK
  42. imply NET_DSA_MT7530_MDIO
  43. + imply NET_DSA_MT7530_MMIO
  44. help
  45. This enables support for the MediaTek MT7530 and MT7531 Ethernet
  46. switch chips. Multi-chip module MT7530 in MT7621AT, MT7621DAT,
  47. @@ -54,6 +55,17 @@ config NET_DSA_MT7530_MDIO
  48. module MT7530 which can be found in the MT7621AT, MT7621DAT,
  49. MT7621ST and MT7623AI SoCs.
  50. +config NET_DSA_MT7530_MMIO
  51. + tristate "MediaTek MT7530 MMIO interface driver"
  52. + depends on NET_DSA_MT7530
  53. + depends on HAS_IOMEM
  54. + help
  55. + This enables support for the built-in Ethernet switch found
  56. + in the MediaTek MT7988 SoC.
  57. + The switch is a similar design as MT7531, but the switch registers
  58. + are directly mapped into the SoCs register space rather than being
  59. + accessible via MDIO.
  60. +
  61. config NET_DSA_MV88E6060
  62. tristate "Marvell 88E6060 ethernet switch chip support"
  63. select NET_DSA_TAG_TRAILER
  64. --- a/drivers/net/dsa/Makefile
  65. +++ b/drivers/net/dsa/Makefile
  66. @@ -8,6 +8,7 @@ endif
  67. obj-$(CONFIG_NET_DSA_LANTIQ_GSWIP) += lantiq_gswip.o
  68. obj-$(CONFIG_NET_DSA_MT7530) += mt7530.o
  69. obj-$(CONFIG_NET_DSA_MT7530_MDIO) += mt7530-mdio.o
  70. +obj-$(CONFIG_NET_DSA_MT7530_MMIO) += mt7530-mmio.o
  71. obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o
  72. obj-$(CONFIG_NET_DSA_RZN1_A5PSW) += rzn1_a5psw.o
  73. obj-$(CONFIG_NET_DSA_SMSC_LAN9303) += lan9303-core.o
  74. --- /dev/null
  75. +++ b/drivers/net/dsa/mt7530-mmio.c
  76. @@ -0,0 +1,101 @@
  77. +// SPDX-License-Identifier: GPL-2.0-only
  78. +
  79. +#include <linux/module.h>
  80. +#include <linux/of_platform.h>
  81. +#include <linux/regmap.h>
  82. +#include <linux/regulator/consumer.h>
  83. +#include <linux/reset.h>
  84. +#include <net/dsa.h>
  85. +
  86. +#include "mt7530.h"
  87. +
  88. +static const struct of_device_id mt7988_of_match[] = {
  89. + { .compatible = "mediatek,mt7988-switch", .data = &mt753x_table[ID_MT7988], },
  90. + { /* sentinel */ },
  91. +};
  92. +MODULE_DEVICE_TABLE(of, mt7988_of_match);
  93. +
  94. +static int
  95. +mt7988_probe(struct platform_device *pdev)
  96. +{
  97. + static struct regmap_config *sw_regmap_config;
  98. + struct mt7530_priv *priv;
  99. + void __iomem *base_addr;
  100. + int ret;
  101. +
  102. + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  103. + if (!priv)
  104. + return -ENOMEM;
  105. +
  106. + priv->bus = NULL;
  107. + priv->dev = &pdev->dev;
  108. +
  109. + ret = mt7530_probe_common(priv);
  110. + if (ret)
  111. + return ret;
  112. +
  113. + priv->rstc = devm_reset_control_get(&pdev->dev, NULL);
  114. + if (IS_ERR(priv->rstc)) {
  115. + dev_err(&pdev->dev, "Couldn't get our reset line\n");
  116. + return PTR_ERR(priv->rstc);
  117. + }
  118. +
  119. + base_addr = devm_platform_ioremap_resource(pdev, 0);
  120. + if (IS_ERR(base_addr)) {
  121. + dev_err(&pdev->dev, "cannot request I/O memory space\n");
  122. + return -ENXIO;
  123. + }
  124. +
  125. + sw_regmap_config = devm_kzalloc(&pdev->dev, sizeof(*sw_regmap_config), GFP_KERNEL);
  126. + if (!sw_regmap_config)
  127. + return -ENOMEM;
  128. +
  129. + sw_regmap_config->name = "switch";
  130. + sw_regmap_config->reg_bits = 16;
  131. + sw_regmap_config->val_bits = 32;
  132. + sw_regmap_config->reg_stride = 4;
  133. + sw_regmap_config->max_register = MT7530_CREV;
  134. + priv->regmap = devm_regmap_init_mmio(&pdev->dev, base_addr, sw_regmap_config);
  135. + if (IS_ERR(priv->regmap))
  136. + return PTR_ERR(priv->regmap);
  137. +
  138. + return dsa_register_switch(priv->ds);
  139. +}
  140. +
  141. +static int
  142. +mt7988_remove(struct platform_device *pdev)
  143. +{
  144. + struct mt7530_priv *priv = platform_get_drvdata(pdev);
  145. +
  146. + if (priv)
  147. + mt7530_remove_common(priv);
  148. +
  149. + return 0;
  150. +}
  151. +
  152. +static void mt7988_shutdown(struct platform_device *pdev)
  153. +{
  154. + struct mt7530_priv *priv = platform_get_drvdata(pdev);
  155. +
  156. + if (!priv)
  157. + return;
  158. +
  159. + dsa_switch_shutdown(priv->ds);
  160. +
  161. + dev_set_drvdata(&pdev->dev, NULL);
  162. +}
  163. +
  164. +static struct platform_driver mt7988_platform_driver = {
  165. + .probe = mt7988_probe,
  166. + .remove = mt7988_remove,
  167. + .shutdown = mt7988_shutdown,
  168. + .driver = {
  169. + .name = "mt7530-mmio",
  170. + .of_match_table = mt7988_of_match,
  171. + },
  172. +};
  173. +module_platform_driver(mt7988_platform_driver);
  174. +
  175. +MODULE_AUTHOR("Daniel Golle <[email protected]>");
  176. +MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch (MMIO)");
  177. +MODULE_LICENSE("GPL");
  178. --- a/drivers/net/dsa/mt7530.c
  179. +++ b/drivers/net/dsa/mt7530.c
  180. @@ -2041,6 +2041,47 @@ static const struct irq_domain_ops mt753
  181. };
  182. static void
  183. +mt7988_irq_mask(struct irq_data *d)
  184. +{
  185. + struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
  186. +
  187. + priv->irq_enable &= ~BIT(d->hwirq);
  188. + mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable);
  189. +}
  190. +
  191. +static void
  192. +mt7988_irq_unmask(struct irq_data *d)
  193. +{
  194. + struct mt7530_priv *priv = irq_data_get_irq_chip_data(d);
  195. +
  196. + priv->irq_enable |= BIT(d->hwirq);
  197. + mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable);
  198. +}
  199. +
  200. +static struct irq_chip mt7988_irq_chip = {
  201. + .name = KBUILD_MODNAME,
  202. + .irq_mask = mt7988_irq_mask,
  203. + .irq_unmask = mt7988_irq_unmask,
  204. +};
  205. +
  206. +static int
  207. +mt7988_irq_map(struct irq_domain *domain, unsigned int irq,
  208. + irq_hw_number_t hwirq)
  209. +{
  210. + irq_set_chip_data(irq, domain->host_data);
  211. + irq_set_chip_and_handler(irq, &mt7988_irq_chip, handle_simple_irq);
  212. + irq_set_nested_thread(irq, true);
  213. + irq_set_noprobe(irq);
  214. +
  215. + return 0;
  216. +}
  217. +
  218. +static const struct irq_domain_ops mt7988_irq_domain_ops = {
  219. + .map = mt7988_irq_map,
  220. + .xlate = irq_domain_xlate_onecell,
  221. +};
  222. +
  223. +static void
  224. mt7530_setup_mdio_irq(struct mt7530_priv *priv)
  225. {
  226. struct dsa_switch *ds = priv->ds;
  227. @@ -2074,8 +2115,15 @@ mt7530_setup_irq(struct mt7530_priv *pri
  228. return priv->irq ? : -EINVAL;
  229. }
  230. - priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS,
  231. - &mt7530_irq_domain_ops, priv);
  232. + if (priv->id == ID_MT7988)
  233. + priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS,
  234. + &mt7988_irq_domain_ops,
  235. + priv);
  236. + else
  237. + priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS,
  238. + &mt7530_irq_domain_ops,
  239. + priv);
  240. +
  241. if (!priv->irq_domain) {
  242. dev_err(dev, "failed to create IRQ domain\n");
  243. return -ENOMEM;
  244. @@ -2574,6 +2622,25 @@ static void mt7531_mac_port_get_caps(str
  245. }
  246. }
  247. +static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port,
  248. + struct phylink_config *config)
  249. +{
  250. + phy_interface_zero(config->supported_interfaces);
  251. +
  252. + switch (port) {
  253. + case 0 ... 4: /* Internal phy */
  254. + __set_bit(PHY_INTERFACE_MODE_INTERNAL,
  255. + config->supported_interfaces);
  256. + break;
  257. +
  258. + case 6:
  259. + __set_bit(PHY_INTERFACE_MODE_INTERNAL,
  260. + config->supported_interfaces);
  261. + config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
  262. + MAC_10000FD;
  263. + }
  264. +}
  265. +
  266. static int
  267. mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
  268. {
  269. @@ -2650,6 +2717,17 @@ static bool mt753x_is_mac_port(u32 port)
  270. }
  271. static int
  272. +mt7988_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
  273. + phy_interface_t interface)
  274. +{
  275. + if (dsa_is_cpu_port(ds, port) &&
  276. + interface == PHY_INTERFACE_MODE_INTERNAL)
  277. + return 0;
  278. +
  279. + return -EINVAL;
  280. +}
  281. +
  282. +static int
  283. mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
  284. phy_interface_t interface)
  285. {
  286. @@ -2719,7 +2797,8 @@ mt753x_phylink_mac_config(struct dsa_swi
  287. switch (port) {
  288. case 0 ... 4: /* Internal phy */
  289. - if (state->interface != PHY_INTERFACE_MODE_GMII)
  290. + if (state->interface != PHY_INTERFACE_MODE_GMII &&
  291. + state->interface != PHY_INTERFACE_MODE_INTERNAL)
  292. goto unsupported;
  293. break;
  294. case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
  295. @@ -2797,7 +2876,8 @@ static void mt753x_phylink_mac_link_up(s
  296. /* MT753x MAC works in 1G full duplex mode for all up-clocked
  297. * variants.
  298. */
  299. - if (interface == PHY_INTERFACE_MODE_TRGMII ||
  300. + if (interface == PHY_INTERFACE_MODE_INTERNAL ||
  301. + interface == PHY_INTERFACE_MODE_TRGMII ||
  302. (phy_interface_mode_is_8023z(interface))) {
  303. speed = SPEED_1000;
  304. duplex = DUPLEX_FULL;
  305. @@ -2877,6 +2957,21 @@ mt7531_cpu_port_config(struct dsa_switch
  306. return 0;
  307. }
  308. +static int
  309. +mt7988_cpu_port_config(struct dsa_switch *ds, int port)
  310. +{
  311. + struct mt7530_priv *priv = ds->priv;
  312. +
  313. + mt7530_write(priv, MT7530_PMCR_P(port),
  314. + PMCR_CPU_PORT_SETTING(priv->id));
  315. +
  316. + mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED,
  317. + PHY_INTERFACE_MODE_INTERNAL, NULL,
  318. + SPEED_10000, DUPLEX_FULL, true, true);
  319. +
  320. + return 0;
  321. +}
  322. +
  323. static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
  324. struct phylink_config *config)
  325. {
  326. @@ -3019,6 +3114,27 @@ static int mt753x_set_mac_eee(struct dsa
  327. return 0;
  328. }
  329. +static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
  330. +{
  331. + return 0;
  332. +}
  333. +
  334. +static int mt7988_setup(struct dsa_switch *ds)
  335. +{
  336. + struct mt7530_priv *priv = ds->priv;
  337. +
  338. + /* Reset the switch */
  339. + reset_control_assert(priv->rstc);
  340. + usleep_range(20, 50);
  341. + reset_control_deassert(priv->rstc);
  342. + usleep_range(20, 50);
  343. +
  344. + /* Reset the switch PHYs */
  345. + mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST);
  346. +
  347. + return mt7531_setup_common(ds);
  348. +}
  349. +
  350. const struct dsa_switch_ops mt7530_switch_ops = {
  351. .get_tag_protocol = mtk_get_tag_protocol,
  352. .setup = mt753x_setup,
  353. @@ -3087,6 +3203,17 @@ const struct mt753x_info mt753x_table[]
  354. .mac_port_get_caps = mt7531_mac_port_get_caps,
  355. .mac_port_config = mt7531_mac_config,
  356. },
  357. + [ID_MT7988] = {
  358. + .id = ID_MT7988,
  359. + .pcs_ops = &mt7530_pcs_ops,
  360. + .sw_setup = mt7988_setup,
  361. + .phy_read = mt7531_ind_phy_read,
  362. + .phy_write = mt7531_ind_phy_write,
  363. + .pad_setup = mt7988_pad_setup,
  364. + .cpu_port_config = mt7988_cpu_port_config,
  365. + .mac_port_get_caps = mt7988_mac_port_get_caps,
  366. + .mac_port_config = mt7988_mac_config,
  367. + },
  368. };
  369. EXPORT_SYMBOL_GPL(mt753x_table);
  370. --- a/drivers/net/dsa/mt7530.h
  371. +++ b/drivers/net/dsa/mt7530.h
  372. @@ -18,6 +18,7 @@ enum mt753x_id {
  373. ID_MT7530 = 0,
  374. ID_MT7621 = 1,
  375. ID_MT7531 = 2,
  376. + ID_MT7988 = 3,
  377. };
  378. #define NUM_TRGMII_CTRL 5
  379. @@ -54,11 +55,11 @@ enum mt753x_id {
  380. #define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16)
  381. #define MT7531_CPU_PMAP_MASK GENMASK(7, 0)
  382. -#define MT753X_MIRROR_REG(id) (((id) == ID_MT7531) ? \
  383. +#define MT753X_MIRROR_REG(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
  384. MT7531_CFC : MT7530_MFC)
  385. -#define MT753X_MIRROR_EN(id) (((id) == ID_MT7531) ? \
  386. +#define MT753X_MIRROR_EN(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
  387. MT7531_MIRROR_EN : MIRROR_EN)
  388. -#define MT753X_MIRROR_MASK(id) (((id) == ID_MT7531) ? \
  389. +#define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
  390. MT7531_MIRROR_MASK : MIRROR_MASK)
  391. /* Registers for BPDU and PAE frame control*/
  392. @@ -322,9 +323,8 @@ enum mt7530_vlan_port_acc_frm {
  393. MT7531_FORCE_DPX | \
  394. MT7531_FORCE_RX_FC | \
  395. MT7531_FORCE_TX_FC)
  396. -#define PMCR_FORCE_MODE_ID(id) (((id) == ID_MT7531) ? \
  397. - MT7531_FORCE_MODE : \
  398. - PMCR_FORCE_MODE)
  399. +#define PMCR_FORCE_MODE_ID(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
  400. + MT7531_FORCE_MODE : PMCR_FORCE_MODE)
  401. #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
  402. PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
  403. PMCR_TX_FC_EN | PMCR_RX_FC_EN | \