790-23-v6.9-net-dsa-mt7530-always-trap-frames-to-active-CPU-port.patch 4.4 KB

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  1. From a385398f77fad9eabe7cdc253e1a356484acc316 Mon Sep 17 00:00:00 2001
  2. From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <[email protected]>
  3. Date: Mon, 22 Jan 2024 08:35:52 +0300
  4. Subject: [PATCH 23/48] net: dsa: mt7530: always trap frames to active CPU port
  5. on MT7530
  6. MIME-Version: 1.0
  7. Content-Type: text/plain; charset=UTF-8
  8. Content-Transfer-Encoding: 8bit
  9. On the MT7530 switch, the CPU_PORT field indicates which CPU port to trap
  10. frames to, regardless of the affinity of the inbound user port.
  11. When multiple CPU ports are in use, if the DSA conduit interface is down,
  12. trapped frames won't be passed to the conduit interface.
  13. To make trapping frames work including this case, implement
  14. ds->ops->conduit_state_change() on this subdriver and set the CPU_PORT
  15. field to the numerically smallest CPU port whose conduit interface is up.
  16. Introduce the active_cpu_ports field to store the information of the active
  17. CPU ports. Correct the macros, CPU_PORT is bits 4 through 6 of the
  18. register.
  19. Add a comment to explain frame trapping for this switch.
  20. Currently, the driver doesn't support the use of multiple CPU ports so this
  21. is not necessarily a bug fix.
  22. Suggested-by: Vladimir Oltean <[email protected]>
  23. Suggested-by: Russell King (Oracle) <[email protected]>
  24. Signed-off-by: Arınç ÜNAL <[email protected]>
  25. Reviewed-by: Vladimir Oltean <[email protected]>
  26. Link: https://lore.kernel.org/r/20240122-for-netnext-mt7530-improvements-1-v3-1-042401f2b279@arinc9.com
  27. Signed-off-by: Jakub Kicinski <[email protected]>
  28. ---
  29. drivers/net/dsa/mt7530.c | 35 +++++++++++++++++++++++++++++++----
  30. drivers/net/dsa/mt7530.h | 6 ++++--
  31. 2 files changed, 35 insertions(+), 6 deletions(-)
  32. --- a/drivers/net/dsa/mt7530.c
  33. +++ b/drivers/net/dsa/mt7530.c
  34. @@ -1064,10 +1064,6 @@ mt753x_cpu_port_enable(struct dsa_switch
  35. mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) |
  36. UNU_FFP(BIT(port)));
  37. - /* Set CPU port number */
  38. - if (priv->id == ID_MT7530 || priv->id == ID_MT7621)
  39. - mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));
  40. -
  41. /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on
  42. * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that
  43. * is affine to the inbound user port.
  44. @@ -3125,6 +3121,36 @@ static int mt753x_set_mac_eee(struct dsa
  45. return 0;
  46. }
  47. +static void
  48. +mt753x_conduit_state_change(struct dsa_switch *ds,
  49. + const struct net_device *conduit,
  50. + bool operational)
  51. +{
  52. + struct dsa_port *cpu_dp = conduit->dsa_ptr;
  53. + struct mt7530_priv *priv = ds->priv;
  54. + int val = 0;
  55. + u8 mask;
  56. +
  57. + /* Set the CPU port to trap frames to for MT7530. Trapped frames will be
  58. + * forwarded to the numerically smallest CPU port whose conduit
  59. + * interface is up.
  60. + */
  61. + if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
  62. + return;
  63. +
  64. + mask = BIT(cpu_dp->index);
  65. +
  66. + if (operational)
  67. + priv->active_cpu_ports |= mask;
  68. + else
  69. + priv->active_cpu_ports &= ~mask;
  70. +
  71. + if (priv->active_cpu_ports)
  72. + val = CPU_EN | CPU_PORT(__ffs(priv->active_cpu_ports));
  73. +
  74. + mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val);
  75. +}
  76. +
  77. static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
  78. {
  79. return 0;
  80. @@ -3179,6 +3205,7 @@ const struct dsa_switch_ops mt7530_switc
  81. .phylink_mac_link_up = mt753x_phylink_mac_link_up,
  82. .get_mac_eee = mt753x_get_mac_eee,
  83. .set_mac_eee = mt753x_set_mac_eee,
  84. + .master_state_change = mt753x_conduit_state_change,
  85. };
  86. EXPORT_SYMBOL_GPL(mt7530_switch_ops);
  87. --- a/drivers/net/dsa/mt7530.h
  88. +++ b/drivers/net/dsa/mt7530.h
  89. @@ -41,8 +41,8 @@ enum mt753x_id {
  90. #define UNU_FFP(x) (((x) & 0xff) << 8)
  91. #define UNU_FFP_MASK UNU_FFP(~0)
  92. #define CPU_EN BIT(7)
  93. -#define CPU_PORT(x) ((x) << 4)
  94. -#define CPU_MASK (0xf << 4)
  95. +#define CPU_PORT_MASK GENMASK(6, 4)
  96. +#define CPU_PORT(x) FIELD_PREP(CPU_PORT_MASK, x)
  97. #define MIRROR_EN BIT(3)
  98. #define MIRROR_PORT(x) ((x) & 0x7)
  99. #define MIRROR_MASK 0x7
  100. @@ -773,6 +773,7 @@ struct mt753x_info {
  101. * @irq_domain: IRQ domain of the switch irq_chip
  102. * @irq_enable: IRQ enable bits, synced to SYS_INT_EN
  103. * @create_sgmii: Pointer to function creating SGMII PCS instance(s)
  104. + * @active_cpu_ports: Holding the active CPU ports
  105. */
  106. struct mt7530_priv {
  107. struct device *dev;
  108. @@ -799,6 +800,7 @@ struct mt7530_priv {
  109. struct irq_domain *irq_domain;
  110. u32 irq_enable;
  111. int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii);
  112. + u8 active_cpu_ports;
  113. };
  114. struct mt7530_hw_vlan_entry {