790-39-v6.9-net-dsa-mt7530-do-not-use-SW_PHY_RST-to-reset-MT7531.patch 1.5 KB

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  1. From 0eb6bc551371070325b6606cc3bed6734ecad87d Mon Sep 17 00:00:00 2001
  2. From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <[email protected]>
  3. Date: Fri, 1 Mar 2024 12:42:59 +0200
  4. Subject: [PATCH 39/48] net: dsa: mt7530: do not use SW_PHY_RST to reset MT7531
  5. switch
  6. MIME-Version: 1.0
  7. Content-Type: text/plain; charset=UTF-8
  8. Content-Transfer-Encoding: 8bit
  9. According to the document MT7531 Reference Manual for Development Board
  10. v1.0, the SW_PHY_RST bit on the SYS_CTRL register doesn't exist for
  11. MT7531. This is likely why forcing link down on all ports is necessary for
  12. MT7531.
  13. Therefore, do not set SW_PHY_RST on mt7531_setup().
  14. Signed-off-by: Arınç ÜNAL <[email protected]>
  15. Signed-off-by: Paolo Abeni <[email protected]>
  16. ---
  17. drivers/net/dsa/mt7530.c | 6 ++----
  18. 1 file changed, 2 insertions(+), 4 deletions(-)
  19. --- a/drivers/net/dsa/mt7530.c
  20. +++ b/drivers/net/dsa/mt7530.c
  21. @@ -2478,14 +2478,12 @@ mt7531_setup(struct dsa_switch *ds)
  22. val = mt7530_read(priv, MT7531_TOP_SIG_SR);
  23. priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
  24. - /* all MACs must be forced link-down before sw reset */
  25. + /* Force link down on all ports before internal reset */
  26. for (i = 0; i < MT7530_NUM_PORTS; i++)
  27. mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
  28. /* Reset the switch through internal reset */
  29. - mt7530_write(priv, MT7530_SYS_CTRL,
  30. - SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
  31. - SYS_CTRL_REG_RST);
  32. + mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST);
  33. if (!priv->p5_sgmii) {
  34. mt7531_pll_setup(priv);