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- From cfa7c85f92cd3814ad9748eb1ab25658c7f7cc67 Mon Sep 17 00:00:00 2001
- From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <[email protected]>
- Date: Wed, 20 Mar 2024 23:45:30 +0300
- Subject: [PATCH 48/48] net: dsa: mt7530: fix improper frames on all 25MHz and
- 40MHz XTAL MT7530
- MIME-Version: 1.0
- Content-Type: text/plain; charset=UTF-8
- Content-Transfer-Encoding: 8bit
- The MT7530 switch after reset initialises with a core clock frequency that
- works with a 25MHz XTAL connected to it. For 40MHz XTAL, the core clock
- frequency must be set to 500MHz.
- The mt7530_pll_setup() function is responsible of setting the core clock
- frequency. Currently, it runs on MT7530 with 25MHz and 40MHz XTAL. This
- causes MT7530 switch with 25MHz XTAL to egress and ingress frames
- improperly.
- Introduce a check to run it only on MT7530 with 40MHz XTAL.
- The core clock frequency is set by writing to a switch PHY's register.
- Access to the PHY's register is done via the MDIO bus the switch is also
- on. Therefore, it works only when the switch makes switch PHYs listen on
- the MDIO bus the switch is on. This is controlled either by the state of
- the ESW_P1_LED_1 pin after reset deassertion or modifying bit 5 of the
- modifiable trap register.
- When ESW_P1_LED_1 is pulled high, PHY indirect access is used. That means
- accessing PHY registers via the PHY indirect access control register of the
- switch.
- When ESW_P1_LED_1 is pulled low, PHY direct access is used. That means
- accessing PHY registers via the MDIO bus the switch is on.
- For MT7530 switch with 40MHz XTAL on a board with ESW_P1_LED_1 pulled high,
- the core clock frequency won't be set to 500MHz, causing the switch to
- egress and ingress frames improperly.
- Run mt7530_pll_setup() after PHY direct access is set on the modifiable
- trap register.
- With these two changes, all MT7530 switches with 25MHz and 40MHz, and
- P1_LED_1 pulled high or low, will egress and ingress frames properly.
- Link: https://github.com/BPI-SINOVOIP/BPI-R2-bsp/blob/4a5dd143f2172ec97a2872fa29c7c4cd520f45b5/linux-mt/drivers/net/ethernet/mediatek/gsw_mt7623.c#L1039
- Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch")
- Signed-off-by: Arınç ÜNAL <[email protected]>
- Link: https://lore.kernel.org/r/20240320-for-net-mt7530-fix-25mhz-xtal-with-direct-phy-access-v1-1-d92f605f1160@arinc9.com
- Signed-off-by: Paolo Abeni <[email protected]>
- ---
- drivers/net/dsa/mt7530.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
- --- a/drivers/net/dsa/mt7530.c
- +++ b/drivers/net/dsa/mt7530.c
- @@ -2259,8 +2259,6 @@ mt7530_setup(struct dsa_switch *ds)
- SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
- SYS_CTRL_REG_RST);
-
- - mt7530_pll_setup(priv);
- -
- /* Lower Tx driving for TRGMII path */
- for (i = 0; i < NUM_TRGMII_CTRL; i++)
- mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
- @@ -2276,6 +2274,9 @@ mt7530_setup(struct dsa_switch *ds)
- val |= MHWTRAP_MANUAL;
- mt7530_write(priv, MT7530_MHWTRAP, val);
-
- + if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ)
- + mt7530_pll_setup(priv);
- +
- mt753x_trap_frames(priv);
-
- /* Enable and reset MIB counters */
|
