422-firmware-qcom-scm-fix-SCM-cold-boot-address.patch 4.2 KB

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  1. From aaa675f07e781e248fcf169ce9a917b48bc2cc9b Mon Sep 17 00:00:00 2001
  2. From: Brian Norris <[email protected]>
  3. Date: Fri, 28 Jul 2023 12:06:23 +0200
  4. Subject: [PATCH 3/3] firmware: qcom: scm: fix SCM cold boot address
  5. This effectively reverts upstream Linux commit 13e77747800e ("firmware:
  6. qcom: scm: Use atomic SCM for cold boot"), because Google WiFi boot
  7. firmwares don't support the atomic variant.
  8. This fixes SMP support for Google WiFi.
  9. Signed-off-by: Brian Norris <[email protected]>
  10. ---
  11. drivers/firmware/qcom_scm-legacy.c | 62 +++++++++++++++++++++++++-----
  12. drivers/firmware/qcom_scm.c | 11 ++++++
  13. 2 files changed, 63 insertions(+), 10 deletions(-)
  14. --- a/drivers/firmware/qcom_scm-legacy.c
  15. +++ b/drivers/firmware/qcom_scm-legacy.c
  16. @@ -13,6 +13,9 @@
  17. #include <linux/arm-smccc.h>
  18. #include <linux/dma-mapping.h>
  19. +#include <asm/cacheflush.h>
  20. +#include <asm/outercache.h>
  21. +
  22. #include "qcom_scm.h"
  23. static DEFINE_MUTEX(qcom_scm_lock);
  24. @@ -117,6 +120,25 @@ static void __scm_legacy_do(const struct
  25. } while (res->a0 == QCOM_SCM_INTERRUPTED);
  26. }
  27. +static void qcom_scm_inv_range(unsigned long start, unsigned long end)
  28. +{
  29. + u32 cacheline_size, ctr;
  30. +
  31. + asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
  32. + cacheline_size = 4 << ((ctr >> 16) & 0xf);
  33. +
  34. + start = round_down(start, cacheline_size);
  35. + end = round_up(end, cacheline_size);
  36. + outer_inv_range(start, end);
  37. + while (start < end) {
  38. + asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)
  39. + : "memory");
  40. + start += cacheline_size;
  41. + }
  42. + dsb();
  43. + isb();
  44. +}
  45. +
  46. /**
  47. * scm_legacy_call() - Sends a command to the SCM and waits for the command to
  48. * finish processing.
  49. @@ -163,10 +185,16 @@ int scm_legacy_call(struct device *dev,
  50. rsp = scm_legacy_command_to_response(cmd);
  51. - cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE);
  52. - if (dma_mapping_error(dev, cmd_phys)) {
  53. - kfree(cmd);
  54. - return -ENOMEM;
  55. + if (dev) {
  56. + cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE);
  57. + if (dma_mapping_error(dev, cmd_phys)) {
  58. + kfree(cmd);
  59. + return -ENOMEM;
  60. + }
  61. + } else {
  62. + cmd_phys = virt_to_phys(cmd);
  63. + __cpuc_flush_dcache_area(cmd, alloc_len);
  64. + outer_flush_range(cmd_phys, cmd_phys + alloc_len);
  65. }
  66. smc.args[0] = 1;
  67. @@ -182,13 +210,26 @@ int scm_legacy_call(struct device *dev,
  68. goto out;
  69. do {
  70. - dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len,
  71. - sizeof(*rsp), DMA_FROM_DEVICE);
  72. + if (dev) {
  73. + dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) +
  74. + cmd_len, sizeof(*rsp),
  75. + DMA_FROM_DEVICE);
  76. + } else {
  77. + unsigned long start = (uintptr_t)cmd + sizeof(*cmd) +
  78. + cmd_len;
  79. + qcom_scm_inv_range(start, start + sizeof(*rsp));
  80. + }
  81. } while (!rsp->is_complete);
  82. - dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +
  83. - le32_to_cpu(rsp->buf_offset),
  84. - resp_len, DMA_FROM_DEVICE);
  85. + if (dev) {
  86. + dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +
  87. + le32_to_cpu(rsp->buf_offset),
  88. + resp_len, DMA_FROM_DEVICE);
  89. + } else {
  90. + unsigned long start = (uintptr_t)cmd + sizeof(*cmd) + cmd_len +
  91. + le32_to_cpu(rsp->buf_offset);
  92. + qcom_scm_inv_range(start, start + resp_len);
  93. + }
  94. if (res) {
  95. res_buf = scm_legacy_get_response_buffer(rsp);
  96. @@ -196,7 +237,8 @@ int scm_legacy_call(struct device *dev,
  97. res->result[i] = le32_to_cpu(res_buf[i]);
  98. }
  99. out:
  100. - dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);
  101. + if (dev)
  102. + dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);
  103. kfree(cmd);
  104. return ret;
  105. }
  106. --- a/drivers/firmware/qcom_scm.c
  107. +++ b/drivers/firmware/qcom_scm.c
  108. @@ -315,6 +315,17 @@ static int qcom_scm_set_boot_addr(void *
  109. desc.args[0] = flags;
  110. desc.args[1] = virt_to_phys(entry);
  111. + /*
  112. + * Factory firmware doesn't support the atomic variant. Non-atomic SCMs
  113. + * require ugly DMA invalidation support that was dropped upstream a
  114. + * while ago. For more info, see:
  115. + *
  116. + * [RFC] qcom_scm: IPQ4019 firmware does not support atomic API?
  117. + * https://lore.kernel.org/linux-arm-msm/20200913201608.GA3162100@bDebian/
  118. + */
  119. + if (of_machine_is_compatible("google,wifi"))
  120. + return qcom_scm_call(__scm ? __scm->dev : NULL, &desc, NULL);
  121. +
  122. return qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL);
  123. }