705-ARM-dts-qcom-ipq4019-Add-description-for-the-IPQESS-.patch 2.9 KB

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  1. From 5b71dbb867680887d47954ce1cc145cb747cbce6 Mon Sep 17 00:00:00 2001
  2. From: Maxime Chevallier <[email protected]>
  3. Date: Fri, 4 Nov 2022 18:41:51 +0100
  4. Subject: [PATCH] ARM: dts: qcom: ipq4019: Add description for the IPQESS
  5. Ethernet controller
  6. The Qualcomm IPQ4019 includes an internal 5 ports switch, which is
  7. connected to the CPU through the internal IPQESS Ethernet controller.
  8. Add support for this internal interface, which is internally connected to a
  9. modified version of the QCA8K Ethernet switch.
  10. This Ethernet controller only support a specific internal interface mode
  11. for connection to the switch.
  12. Signed-off-by: Maxime Chevallier <[email protected]>
  13. Reviewed-by: Krzysztof Kozlowski <[email protected]>
  14. ---
  15. arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 48 +++++++++++++++++++++++++++++
  16. 1 file changed, 48 insertions(+)
  17. --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
  18. +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
  19. @@ -596,6 +596,54 @@
  20. status = "disabled";
  21. };
  22. + gmac: ethernet@c080000 {
  23. + compatible = "qcom,ipq4019-ess-edma";
  24. + reg = <0xc080000 0x8000>;
  25. + resets = <&gcc ESS_RESET>;
  26. + reset-names = "ess";
  27. + clocks = <&gcc GCC_ESS_CLK>;
  28. + clock-names = "ess";
  29. + interrupts = <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>,
  30. + <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
  31. + <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
  32. + <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>,
  33. + <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>,
  34. + <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>,
  35. + <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>,
  36. + <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>,
  37. + <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
  38. + <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
  39. + <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
  40. + <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
  41. + <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
  42. + <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
  43. + <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
  44. + <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
  45. + <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
  46. + <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
  47. + <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
  48. + <GIC_SPI 243 IRQ_TYPE_EDGE_RISING>,
  49. + <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
  50. + <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
  51. + <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
  52. + <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
  53. + <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
  54. + <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
  55. + <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
  56. + <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
  57. + <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
  58. + <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>,
  59. + <GIC_SPI 254 IRQ_TYPE_EDGE_RISING>,
  60. + <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>;
  61. + phy-mode = "internal";
  62. + status = "disabled";
  63. + fixed-link {
  64. + speed = <1000>;
  65. + full-duplex;
  66. + pause;
  67. + };
  68. + };
  69. +
  70. mdio: mdio@90000 {
  71. #address-cells = <1>;
  72. #size-cells = <0>;