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122-05-clk-qcom-clk-krait-generilize-div-functions.patch 4.8 KB

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  1. From 908c361b3c3a139eb3e6a798cb620a6da7514d5c Mon Sep 17 00:00:00 2001
  2. From: Christian Marangi <[email protected]>
  3. Date: Fri, 23 Sep 2022 19:05:39 +0200
  4. Subject: [PATCH 2/4] clk: qcom: clk-krait: generilize div functions
  5. Generilize div functions and remove hardcode to a divisor of 2.
  6. This is just a cleanup and permit to make it more clear the settings of
  7. the devisor when used by the krait-cc driver.
  8. Signed-off-by: Christian Marangi <[email protected]>
  9. ---
  10. drivers/clk/qcom/clk-krait.c | 57 ++++++++++++++++++++----------------
  11. drivers/clk/qcom/clk-krait.h | 11 ++++---
  12. drivers/clk/qcom/krait-cc.c | 7 +++--
  13. 3 files changed, 42 insertions(+), 33 deletions(-)
  14. --- a/drivers/clk/qcom/clk-krait.c
  15. +++ b/drivers/clk/qcom/clk-krait.c
  16. @@ -97,53 +97,57 @@ const struct clk_ops krait_mux_clk_ops =
  17. EXPORT_SYMBOL_GPL(krait_mux_clk_ops);
  18. /* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */
  19. -static int krait_div2_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
  20. +static int krait_div_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
  21. {
  22. - req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), req->rate * 2);
  23. - req->rate = DIV_ROUND_UP(req->best_parent_rate, 2);
  24. + struct krait_div_clk *d = to_krait_div_clk(hw);
  25. +
  26. + req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
  27. + req->rate * d->divisor);
  28. + req->rate = DIV_ROUND_UP(req->best_parent_rate, d->divisor);
  29. return 0;
  30. }
  31. -static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,
  32. +static int krait_div_set_rate(struct clk_hw *hw, unsigned long rate,
  33. unsigned long parent_rate)
  34. {
  35. - struct krait_div2_clk *d = to_krait_div2_clk(hw);
  36. + struct krait_div_clk *d = to_krait_div_clk(hw);
  37. + u8 div_val = krait_div_to_val(d->divisor);
  38. unsigned long flags;
  39. - u32 val;
  40. - u32 mask = BIT(d->width) - 1;
  41. -
  42. - if (d->lpl)
  43. - mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift;
  44. - else
  45. - mask <<= d->shift;
  46. + u32 regval;
  47. spin_lock_irqsave(&krait_clock_reg_lock, flags);
  48. - val = krait_get_l2_indirect_reg(d->offset);
  49. - val &= ~mask;
  50. - krait_set_l2_indirect_reg(d->offset, val);
  51. + regval = krait_get_l2_indirect_reg(d->offset);
  52. +
  53. + regval &= ~(d->mask << d->shift);
  54. + regval |= (div_val & d->mask) << d->shift;
  55. +
  56. + if (d->lpl) {
  57. + regval &= ~(d->mask << (d->shift + LPL_SHIFT));
  58. + regval |= (div_val & d->mask) << (d->shift + LPL_SHIFT);
  59. + }
  60. +
  61. + krait_set_l2_indirect_reg(d->offset, regval);
  62. spin_unlock_irqrestore(&krait_clock_reg_lock, flags);
  63. return 0;
  64. }
  65. static unsigned long
  66. -krait_div2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
  67. +krait_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
  68. {
  69. - struct krait_div2_clk *d = to_krait_div2_clk(hw);
  70. - u32 mask = BIT(d->width) - 1;
  71. + struct krait_div_clk *d = to_krait_div_clk(hw);
  72. u32 div;
  73. div = krait_get_l2_indirect_reg(d->offset);
  74. div >>= d->shift;
  75. - div &= mask;
  76. - div = (div + 1) * 2;
  77. + div &= d->mask;
  78. - return DIV_ROUND_UP(parent_rate, div);
  79. + return DIV_ROUND_UP(parent_rate, krait_val_to_div(div));
  80. }
  81. -const struct clk_ops krait_div2_clk_ops = {
  82. - .determine_rate = krait_div2_determine_rate,
  83. - .set_rate = krait_div2_set_rate,
  84. - .recalc_rate = krait_div2_recalc_rate,
  85. +const struct clk_ops krait_div_clk_ops = {
  86. + .determine_rate = krait_div_determine_rate,
  87. + .set_rate = krait_div_set_rate,
  88. + .recalc_rate = krait_div_recalc_rate,
  89. };
  90. -EXPORT_SYMBOL_GPL(krait_div2_clk_ops);
  91. +EXPORT_SYMBOL_GPL(krait_div_clk_ops);
  92. --- a/drivers/clk/qcom/clk-krait.h
  93. +++ b/drivers/clk/qcom/clk-krait.h
  94. @@ -25,17 +25,20 @@ struct krait_mux_clk {
  95. extern const struct clk_ops krait_mux_clk_ops;
  96. -struct krait_div2_clk {
  97. +struct krait_div_clk {
  98. u32 offset;
  99. - u8 width;
  100. + u32 mask;
  101. + u8 divisor;
  102. u32 shift;
  103. bool lpl;
  104. struct clk_hw hw;
  105. };
  106. -#define to_krait_div2_clk(_hw) container_of(_hw, struct krait_div2_clk, hw)
  107. +#define to_krait_div_clk(_hw) container_of(_hw, struct krait_div_clk, hw)
  108. +#define krait_div_to_val(_div) ((_div) / 2) - 1
  109. +#define krait_val_to_div(_val) ((_val) + 1) * 2
  110. -extern const struct clk_ops krait_div2_clk_ops;
  111. +extern const struct clk_ops krait_div_clk_ops;
  112. #endif
  113. --- a/drivers/clk/qcom/krait-cc.c
  114. +++ b/drivers/clk/qcom/krait-cc.c
  115. @@ -86,11 +86,11 @@ static int krait_notifier_register(struc
  116. static struct clk_hw *
  117. krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
  118. {
  119. - struct krait_div2_clk *div;
  120. + struct krait_div_clk *div;
  121. static struct clk_parent_data p_data[1];
  122. struct clk_init_data init = {
  123. .num_parents = ARRAY_SIZE(p_data),
  124. - .ops = &krait_div2_clk_ops,
  125. + .ops = &krait_div_clk_ops,
  126. .flags = CLK_SET_RATE_PARENT,
  127. };
  128. struct clk_hw *clk;
  129. @@ -101,7 +101,8 @@ krait_add_div(struct device *dev, int id
  130. if (!div)
  131. return ERR_PTR(-ENOMEM);
  132. - div->width = 2;
  133. + div->mask = 0x3;
  134. + div->divisor = 2;
  135. div->shift = 6;
  136. div->lpl = id >= 0;
  137. div->offset = offset;