mt7622-dlink-eagle-pro-ai-ax3200-a1.dtsi 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. /dts-v1/;
  3. #include "mt7622.dtsi"
  4. #include "mt6380.dtsi"
  5. #include <dt-bindings/gpio/gpio.h>
  6. #include <dt-bindings/input/input.h>
  7. / {
  8. aliases {
  9. serial0 = &uart0;
  10. label-mac-device = &gmac0;
  11. };
  12. chosen {
  13. stdout-path = "serial0:115200n8";
  14. bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 swiotlb=512";
  15. };
  16. cpus {
  17. cpu@0 {
  18. proc-supply = <&mt6380_vcpu_reg>;
  19. sram-supply = <&mt6380_vm_reg>;
  20. };
  21. cpu@1 {
  22. proc-supply = <&mt6380_vcpu_reg>;
  23. sram-supply = <&mt6380_vm_reg>;
  24. };
  25. };
  26. gpio-keys {
  27. compatible = "gpio-keys";
  28. button-reset {
  29. gpios = <&pio 0 GPIO_ACTIVE_LOW>;
  30. label = "reset";
  31. linux,code = <KEY_RESTART>;
  32. };
  33. button-wps {
  34. gpios = <&pio 102 GPIO_ACTIVE_LOW>;
  35. label = "wps";
  36. linux,code = <KEY_WPS_BUTTON>;
  37. };
  38. };
  39. memory {
  40. reg = <0 0x40000000 0 0x40000000>;
  41. };
  42. };
  43. &bch {
  44. status = "okay";
  45. };
  46. &eth {
  47. pinctrl-names = "default";
  48. pinctrl-0 = <&eth_pins>;
  49. status = "okay";
  50. gmac0: mac@0 {
  51. compatible = "mediatek,eth-mac";
  52. phy-mode = "2500base-x";
  53. reg = <0>;
  54. nvmem-cells = <&macaddr_odm 1>;
  55. nvmem-cell-names = "mac-address";
  56. fixed-link {
  57. full-duplex;
  58. pause;
  59. speed = <2500>;
  60. };
  61. };
  62. mdio-bus {
  63. #address-cells = <1>;
  64. #size-cells = <0>;
  65. switch: switch@0 {
  66. compatible = "mediatek,mt7531";
  67. reg = <0>;
  68. interrupt-controller;
  69. #interrupt-cells = <1>;
  70. interrupt-parent = <&pio>;
  71. interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
  72. reset-gpios = <&pio 54 0>;
  73. ports {
  74. wan: port@4 {
  75. reg = <4>;
  76. label = "wan";
  77. nvmem-cells = <&macaddr_odm 0>;
  78. nvmem-cell-names = "mac-address";
  79. };
  80. port@6 {
  81. reg = <6>;
  82. ethernet = <&gmac0>;
  83. phy-mode = "2500base-x";
  84. fixed-link {
  85. speed = <2500>;
  86. full-duplex;
  87. pause;
  88. };
  89. };
  90. };
  91. };
  92. };
  93. };
  94. &pcie0 {
  95. pinctrl-names = "default";
  96. pinctrl-0 = <&pcie0_pins>;
  97. status = "okay";
  98. };
  99. &pcie1 {
  100. pinctrl-names = "default";
  101. pinctrl-0 = <&pcie1_pins>;
  102. status = "okay";
  103. };
  104. &pio {
  105. epa_elna_pins: epa-elna-pins {
  106. mux {
  107. function = "antsel";
  108. groups = "antsel0", "antsel1", "antsel2", "antsel3",
  109. "antsel4", "antsel5", "antsel6", "antsel7",
  110. "antsel8", "antsel9", "antsel12", "antsel13",
  111. "antsel14", "antsel15", "antsel16", "antsel17";
  112. };
  113. };
  114. eth_pins: eth-pins {
  115. mux {
  116. function = "eth";
  117. groups = "mdc_mdio", "rgmii_via_gmac2";
  118. };
  119. };
  120. pcie0_pins: pcie0-pins {
  121. mux {
  122. function = "pcie";
  123. groups = "pcie0_pad_perst",
  124. "pcie0_1_waken",
  125. "pcie0_1_clkreq";
  126. };
  127. };
  128. pcie1_pins: pcie1-pins {
  129. mux {
  130. function = "pcie";
  131. groups = "pcie1_pad_perst",
  132. "pcie1_0_waken",
  133. "pcie1_0_clkreq";
  134. };
  135. };
  136. pmic_bus_pins: pmic-bus-pins {
  137. mux {
  138. function = "pmic";
  139. groups = "pmic_bus";
  140. };
  141. };
  142. /* Serial NAND is shared pin with SPI-NOR */
  143. serial_nand_pins: serial-nand-pins {
  144. mux {
  145. function = "flash";
  146. groups = "snfi";
  147. };
  148. };
  149. uart0_pins: uart0-pins {
  150. mux {
  151. function = "uart";
  152. groups = "uart0_0_tx_rx";
  153. };
  154. };
  155. watchdog_pins: watchdog-pins {
  156. mux {
  157. function = "watchdog";
  158. groups = "watchdog";
  159. };
  160. };
  161. };
  162. &pwrap {
  163. pinctrl-names = "default";
  164. pinctrl-0 = <&pmic_bus_pins>;
  165. status = "okay";
  166. };
  167. &rtc {
  168. status = "disabled";
  169. };
  170. &sata {
  171. status = "disabled";
  172. };
  173. &sata_phy {
  174. status = "disabled";
  175. };
  176. &slot0 {
  177. wmac1: mt7915@0,0 {
  178. reg = <0x0000 0 0 0 0>;
  179. ieee80211-freq-limit = <5000000 6000000>;
  180. mediatek,mtd-eeprom = <&factory 0x05000>;
  181. nvmem-cells = <&macaddr_odm 3>;
  182. nvmem-cell-names = "mac-address";
  183. };
  184. };
  185. &snfi {
  186. pinctrl-names = "default";
  187. pinctrl-0 = <&serial_nand_pins>;
  188. status = "okay";
  189. snand: flash@0 {
  190. compatible = "spi-nand";
  191. mediatek,bmt-table-size = <0x1000>;
  192. mediatek,bmt-v2;
  193. nand-ecc-engine = <&snfi>;
  194. reg = <0>;
  195. spi-rx-bus-width = <4>;
  196. spi-tx-bus-width = <4>;
  197. partitions {
  198. compatible = "fixed-partitions";
  199. #address-cells = <1>;
  200. #size-cells = <1>;
  201. partition@0 {
  202. label = "Preloader";
  203. reg = <0x00000000 0x00080000>;
  204. read-only;
  205. };
  206. partition@80000 {
  207. label = "ATF";
  208. reg = <0x00080000 0x00040000>;
  209. read-only;
  210. };
  211. partition@C0000 {
  212. label = "Bootloader";
  213. reg = <0x000C0000 0x00080000>;
  214. read-only;
  215. };
  216. partition@140000 {
  217. label = "BootConfig";
  218. reg = <0x00140000 0x00040000>;
  219. };
  220. partition@180000 {
  221. label = "Odm";
  222. reg = <0x00180000 0x00040000>;
  223. read-only;
  224. odm_partition: nvmem-layout {
  225. compatible = "fixed-layout";
  226. };
  227. };
  228. config1: partition@1C0000 {
  229. compatible = "nvmem-cells";
  230. label = "Config1";
  231. reg = <0x001C0000 0x00080000>;
  232. read-only;
  233. };
  234. partition@240000 {
  235. label = "Config2";
  236. reg = <0x00240000 0x00080000>;
  237. read-only;
  238. };
  239. partition@2C0000 {
  240. label = "Kernel1";
  241. reg = <0x002C0000 0x02D00000>;
  242. compatible = "denx,fit";
  243. openwrt,cmdline-match = "boot_part=Kernel1";
  244. partition@0 {
  245. label = "kernel";
  246. reg = <0x00000000 0x00800000>;
  247. };
  248. partition@800000 {
  249. label = "ubi";
  250. reg = <0x00800000 0x02500000>;
  251. };
  252. };
  253. partition@2FC0000 {
  254. label = "Kernel2";
  255. reg = <0x02FC0000 0x02D00000>;
  256. compatible = "denx,fit";
  257. openwrt,cmdline-match = "boot_part=Kernel2";
  258. partition@0 {
  259. label = "kernel";
  260. reg = <0x00000000 0x00800000>;
  261. };
  262. partition@800000 {
  263. label = "ubi";
  264. reg = <0x00800000 0x02500000>;
  265. };
  266. };
  267. factory: partition@5CC0000 {
  268. label = "Factory";
  269. reg = <0x05CC0000 0x00100000>;
  270. read-only;
  271. };
  272. partition@5DC0000 {
  273. label = "Mydlink";
  274. reg = <0x05DC0000 0x00200000>;
  275. read-only;
  276. };
  277. partition@5FC0000 {
  278. label = "Storage";
  279. reg = <0x05FC0000 0x00300000>;
  280. read-only;
  281. };
  282. };
  283. };
  284. };
  285. &ssusb {
  286. status = "disabled";
  287. };
  288. &u3phy {
  289. status = "disabled";
  290. };
  291. &uart0 {
  292. pinctrl-names = "default";
  293. pinctrl-0 = <&uart0_pins>;
  294. status = "okay";
  295. };
  296. &watchdog {
  297. pinctrl-names = "default";
  298. pinctrl-0 = <&watchdog_pins>;
  299. status = "okay";
  300. };
  301. &wmac {
  302. pinctrl-names = "default";
  303. pinctrl-0 = <&epa_elna_pins>;
  304. mediatek,mtd-eeprom = <&factory 0x0000>;
  305. nvmem-cells = <&macaddr_odm 2>;
  306. nvmem-cell-names = "mac-address";
  307. status = "okay";
  308. };