mt7622-elecom-wrc-2533gent.dts 9.9 KB

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  1. // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
  2. /*
  3. * Copyright (c) 2017 MediaTek Inc.
  4. * Author: Ming Huang <[email protected]>
  5. * Sean Wang <[email protected]>
  6. */
  7. /dts-v1/;
  8. #include <dt-bindings/input/input.h>
  9. #include <dt-bindings/gpio/gpio.h>
  10. #include "mt7622.dtsi"
  11. #include "mt6380.dtsi"
  12. / {
  13. model = "Elecom WRC-2533";
  14. compatible = "elecom,wrc-2533gent", "mediatek,mt7622";
  15. aliases {
  16. led-boot = &led_power;
  17. led-failsafe = &led_power;
  18. led-running = &led_power;
  19. led-upgrade = &led_power;
  20. serial0 = &uart0;
  21. };
  22. chosen {
  23. stdout-path = "serial0:115200n8";
  24. bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512 console=ttyS0,115200n8";
  25. };
  26. cpus {
  27. cpu@0 {
  28. proc-supply = <&mt6380_vcpu_reg>;
  29. sram-supply = <&mt6380_vm_reg>;
  30. };
  31. cpu@1 {
  32. proc-supply = <&mt6380_vcpu_reg>;
  33. sram-supply = <&mt6380_vm_reg>;
  34. };
  35. };
  36. gpio-keys {
  37. compatible = "gpio-keys";
  38. poll-interval = <100>;
  39. wps {
  40. label = "wps";
  41. linux,code = <KEY_WPS_BUTTON>;
  42. gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
  43. };
  44. factory {
  45. label = "factory";
  46. linux,code = <KEY_WPS_BUTTON>;
  47. gpios = <&pio 102 GPIO_ACTIVE_LOW>;
  48. };
  49. switch0 {
  50. label = "switch0";
  51. gpios = <&pio 1 GPIO_ACTIVE_LOW>;
  52. linux,code = <BTN_0>;
  53. linux,input-type = <EV_SW>;
  54. };
  55. switch1 {
  56. label = "switch1";
  57. gpios = <&pio 16 GPIO_ACTIVE_LOW>;
  58. linux,code = <BTN_1>;
  59. linux,input-type = <EV_SW>;
  60. };
  61. switch2 {
  62. label = "switch2";
  63. gpios = <&pio 17 GPIO_ACTIVE_LOW>;
  64. linux,code = <BTN_2>;
  65. linux,input-type = <EV_SW>;
  66. };
  67. switch3 {
  68. label = "switch3";
  69. gpios = <&pio 18 GPIO_ACTIVE_LOW>;
  70. linux,code = <BTN_3>;
  71. linux,input-type = <EV_SW>;
  72. };
  73. };
  74. leds {
  75. compatible = "gpio-leds";
  76. led_power: power_g {
  77. label = "wrc-2533:green:power";
  78. gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
  79. };
  80. power_b {
  81. label = "wrc-2533:blue:power";
  82. gpios = <&pio 19 GPIO_ACTIVE_HIGH>;
  83. };
  84. power_r {
  85. label = "wrc-2533:red:power";
  86. gpios = <&pio 73 GPIO_ACTIVE_HIGH>;
  87. };
  88. usb {
  89. label = "wrc-2533:blue:usb";
  90. gpios = <&pio 74 GPIO_ACTIVE_HIGH>;
  91. };
  92. wps {
  93. label = "wrc-2533:red:wps";
  94. gpios = <&pio 76 GPIO_ACTIVE_LOW>;
  95. };
  96. wifi2 {
  97. label = "wrc-2533:blue:wifi2g";
  98. gpios = <&pio 85 GPIO_ACTIVE_LOW>;
  99. };
  100. wifi5 {
  101. label = "wrc-2533:blue:wifi5g";
  102. gpios = <&pio 91 GPIO_ACTIVE_LOW>;
  103. };
  104. };
  105. reg_usb_vbus: regulator {
  106. compatible = "regulator-fixed";
  107. regulator-name = "usb_vbus";
  108. regulator-min-microvolt = <5000000>;
  109. regulator-max-microvolt = <5000000>;
  110. gpio = <&pio 22 GPIO_ACTIVE_LOW>;
  111. enable-active-high;
  112. };
  113. memory {
  114. reg = <0 0x40000000 0 0x3F000000>;
  115. };
  116. reg_1p8v: regulator-1p8v {
  117. compatible = "regulator-fixed";
  118. regulator-name = "fixed-1.8V";
  119. regulator-min-microvolt = <1800000>;
  120. regulator-max-microvolt = <1800000>;
  121. regulator-always-on;
  122. };
  123. reg_3p3v: regulator-3p3v {
  124. compatible = "regulator-fixed";
  125. regulator-name = "fixed-3.3V";
  126. regulator-min-microvolt = <3300000>;
  127. regulator-max-microvolt = <3300000>;
  128. regulator-boot-on;
  129. regulator-always-on;
  130. };
  131. rtkgsw: rtkgsw@0 {
  132. compatible = "mediatek,rtk-gsw";
  133. mediatek,ethsys = <&ethsys>;
  134. mediatek,mdio = <&mdio>;
  135. mediatek,reset-pin = <&pio 54 0>;
  136. status = "okay";
  137. };
  138. };
  139. &pcie0 {
  140. pinctrl-names = "default";
  141. pinctrl-0 = <&pcie0_pins>;
  142. status = "okay";
  143. };
  144. &slot0 {
  145. mt7615@0,0 {
  146. reg = <0x0000 0 0 0 0>;
  147. mediatek,mtd-eeprom = <&factory 0x05000>;
  148. };
  149. };
  150. &pio {
  151. /* eMMC is shared pin with parallel NAND */
  152. emmc_pins_default: emmc-pins-default {
  153. mux {
  154. function = "emmc", "emmc_rst";
  155. groups = "emmc";
  156. };
  157. /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
  158. * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
  159. * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
  160. */
  161. conf-cmd-dat {
  162. pins = "NDL0", "NDL1", "NDL2",
  163. "NDL3", "NDL4", "NDL5",
  164. "NDL6", "NDL7", "NRB";
  165. input-enable;
  166. bias-pull-up;
  167. };
  168. conf-clk {
  169. pins = "NCLE";
  170. bias-pull-down;
  171. };
  172. };
  173. emmc_pins_uhs: emmc-pins-uhs {
  174. mux {
  175. function = "emmc";
  176. groups = "emmc";
  177. };
  178. conf-cmd-dat {
  179. pins = "NDL0", "NDL1", "NDL2",
  180. "NDL3", "NDL4", "NDL5",
  181. "NDL6", "NDL7", "NRB";
  182. input-enable;
  183. drive-strength = <4>;
  184. bias-pull-up;
  185. };
  186. conf-clk {
  187. pins = "NCLE";
  188. drive-strength = <4>;
  189. bias-pull-down;
  190. };
  191. };
  192. eth_pins: eth-pins {
  193. mux {
  194. function = "eth";
  195. groups = "mdc_mdio", "rgmii_via_gmac2";
  196. };
  197. };
  198. i2c1_pins: i2c1-pins {
  199. mux {
  200. function = "i2c";
  201. groups = "i2c1_0";
  202. };
  203. };
  204. i2c2_pins: i2c2-pins {
  205. mux {
  206. function = "i2c";
  207. groups = "i2c2_0";
  208. };
  209. };
  210. i2s1_pins: i2s1-pins {
  211. mux {
  212. function = "i2s";
  213. groups = "i2s_out_mclk_bclk_ws",
  214. "i2s1_in_data",
  215. "i2s1_out_data";
  216. };
  217. conf {
  218. pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
  219. "I2S_WS", "I2S_MCLK";
  220. drive-strength = <12>;
  221. bias-pull-down;
  222. };
  223. };
  224. irrx_pins: irrx-pins {
  225. mux {
  226. function = "ir";
  227. groups = "ir_1_rx";
  228. };
  229. };
  230. irtx_pins: irtx-pins {
  231. mux {
  232. function = "ir";
  233. groups = "ir_1_tx";
  234. };
  235. };
  236. /* Parallel nand is shared pin with eMMC */
  237. parallel_nand_pins: parallel-nand-pins {
  238. mux {
  239. function = "flash";
  240. groups = "par_nand";
  241. };
  242. };
  243. pcie0_pins: pcie0-pins {
  244. mux {
  245. function = "pcie";
  246. groups = "pcie0_pad_perst",
  247. "pcie0_1_waken",
  248. "pcie0_1_clkreq";
  249. };
  250. };
  251. pcie1_pins: pcie1-pins {
  252. mux {
  253. function = "pcie";
  254. groups = "pcie1_pad_perst",
  255. "pcie1_0_waken",
  256. "pcie1_0_clkreq";
  257. };
  258. };
  259. pmic_bus_pins: pmic-bus-pins {
  260. mux {
  261. function = "pmic";
  262. groups = "pmic_bus";
  263. };
  264. };
  265. pwm7_pins: pwm1-2-pins {
  266. mux {
  267. function = "pwm";
  268. groups = "pwm_ch7_2";
  269. };
  270. };
  271. wled_pins: wled-pins {
  272. mux {
  273. function = "led";
  274. groups = "wled";
  275. };
  276. };
  277. sd0_pins_default: sd0-pins-default {
  278. mux {
  279. function = "sd";
  280. groups = "sd_0";
  281. };
  282. /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
  283. * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
  284. * DAT2, DAT3, CMD, CLK for SD respectively.
  285. */
  286. conf-cmd-data {
  287. pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
  288. "I2S2_IN","I2S4_OUT";
  289. input-enable;
  290. drive-strength = <8>;
  291. bias-pull-up;
  292. };
  293. conf-clk {
  294. pins = "I2S3_OUT";
  295. drive-strength = <12>;
  296. bias-pull-down;
  297. };
  298. conf-cd {
  299. pins = "TXD3";
  300. bias-pull-up;
  301. };
  302. };
  303. sd0_pins_uhs: sd0-pins-uhs {
  304. mux {
  305. function = "sd";
  306. groups = "sd_0";
  307. };
  308. conf-cmd-data {
  309. pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
  310. "I2S2_IN","I2S4_OUT";
  311. input-enable;
  312. bias-pull-up;
  313. };
  314. conf-clk {
  315. pins = "I2S3_OUT";
  316. bias-pull-down;
  317. };
  318. };
  319. /* Serial NAND is shared pin with SPI-NOR */
  320. serial_nand_pins: serial-nand-pins {
  321. mux {
  322. function = "flash";
  323. groups = "snfi";
  324. };
  325. };
  326. spic0_pins: spic0-pins {
  327. mux {
  328. function = "spi";
  329. groups = "spic0_0";
  330. };
  331. };
  332. spic1_pins: spic1-pins {
  333. mux {
  334. function = "spi";
  335. groups = "spic1_0";
  336. };
  337. };
  338. /* SPI-NOR is shared pin with serial NAND */
  339. spi_nor_pins: spi-nor-pins {
  340. mux {
  341. function = "flash";
  342. groups = "spi_nor";
  343. };
  344. };
  345. /* serial NAND is shared pin with SPI-NOR */
  346. serial_nand_pins: serial-nand-pins {
  347. mux {
  348. function = "flash";
  349. groups = "snfi";
  350. };
  351. };
  352. uart0_pins: uart0-pins {
  353. mux {
  354. function = "uart";
  355. groups = "uart0_0_tx_rx" ;
  356. };
  357. };
  358. uart2_pins: uart2-pins {
  359. mux {
  360. function = "uart";
  361. groups = "uart2_1_tx_rx" ;
  362. };
  363. };
  364. watchdog_pins: watchdog-pins {
  365. mux {
  366. function = "watchdog";
  367. groups = "watchdog";
  368. };
  369. };
  370. };
  371. &btif {
  372. status = "disabled";
  373. };
  374. &cir {
  375. pinctrl-names = "default";
  376. pinctrl-0 = <&irrx_pins>;
  377. status = "okay";
  378. };
  379. &eth {
  380. status = "okay";
  381. pinctrl-names = "default";
  382. pinctrl-0 = <&eth_pins>;
  383. gmac0: mac@0 {
  384. compatible = "mediatek,eth-mac";
  385. reg = <0>;
  386. phy-mode = "sgmii";
  387. fixed-link {
  388. speed = <1000>;
  389. full-duplex;
  390. pause;
  391. };
  392. };
  393. gmac1: mac@1 {
  394. compatible = "mediatek,eth-mac";
  395. reg = <1>;
  396. phy-mode = "rgmii";
  397. fixed-link {
  398. speed = <1000>;
  399. full-duplex;
  400. pause;
  401. };
  402. };
  403. mdio: mdio-bus {
  404. #address-cells = <1>;
  405. #size-cells = <0>;
  406. };
  407. };
  408. &i2c1 {
  409. pinctrl-names = "default";
  410. pinctrl-0 = <&i2c1_pins>;
  411. status = "okay";
  412. };
  413. &i2c2 {
  414. pinctrl-names = "default";
  415. pinctrl-0 = <&i2c2_pins>;
  416. status = "okay";
  417. };
  418. &pwm {
  419. pinctrl-names = "default";
  420. pinctrl-0 = <&pwm7_pins>;
  421. status = "okay";
  422. };
  423. &pwrap {
  424. pinctrl-names = "default";
  425. pinctrl-0 = <&pmic_bus_pins>;
  426. status = "okay";
  427. };
  428. &bch {
  429. status = "okay";
  430. };
  431. &snfi {
  432. pinctrl-names = "default";
  433. pinctrl-0 = <&serial_nand_pins>;
  434. status = "okay";
  435. flash@0 {
  436. compatible = "spi-nand";
  437. reg = <0>;
  438. spi-tx-bus-width = <4>;
  439. spi-rx-bus-width = <4>;
  440. nand-ecc-engine = <&snfi>;
  441. partitions {
  442. compatible = "fixed-partitions";
  443. #address-cells = <1>;
  444. #size-cells = <1>;
  445. partition@0 {
  446. label = "Preloader";
  447. reg = <0x00000 0x0080000>;
  448. read-only;
  449. };
  450. partition@80000 {
  451. label = "ATF";
  452. reg = <0x80000 0x0040000>;
  453. read-only;
  454. };
  455. partition@c0000 {
  456. label = "uboot";
  457. reg = <0xc0000 0x0080000>;
  458. read-only;
  459. };
  460. partition@140000 {
  461. label = "uboot-env";
  462. reg = <0x140000 0x0080000>;
  463. read-only;
  464. };
  465. factory: partition@1c0000 {
  466. label = "factory";
  467. reg = <0x1c0000 0x0040000>;
  468. read-only;
  469. };
  470. partition@200000 {
  471. label = "firmware";
  472. reg = <0x200000 0x2000000>;
  473. };
  474. partition@2200000 {
  475. label = "reserved";
  476. reg = <0x2200000 0x4000000>;
  477. };
  478. };
  479. };
  480. };
  481. &spi0 {
  482. pinctrl-names = "default";
  483. pinctrl-0 = <&spic0_pins>;
  484. status = "okay";
  485. };
  486. &spi1 {
  487. pinctrl-names = "default";
  488. pinctrl-0 = <&spic1_pins>;
  489. status = "okay";
  490. };
  491. &ssusb {
  492. vusb33-supply = <&reg_3p3v>;
  493. vbus-supply = <&reg_usb_vbus>;
  494. status = "okay";
  495. };
  496. &u3phy {
  497. status = "okay";
  498. };
  499. &uart0 {
  500. pinctrl-names = "default";
  501. pinctrl-0 = <&uart0_pins>;
  502. status = "okay";
  503. };
  504. &uart2 {
  505. pinctrl-names = "default";
  506. pinctrl-0 = <&uart2_pins>;
  507. status = "okay";
  508. };
  509. &watchdog {
  510. pinctrl-names = "default";
  511. pinctrl-0 = <&watchdog_pins>;
  512. status = "okay";
  513. };
  514. &wmac {
  515. mediatek,mtd-eeprom = <&factory 0x0000>;
  516. status = "okay";
  517. };