mt7981a-comfast-cf-e393ax.dts 4.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  2. /dts-v1/;
  3. #include "mt7981.dtsi"
  4. / {
  5. model = "COMFAST CF-E393AX";
  6. compatible = "comfast,cf-e393ax", "mediatek,mt7981";
  7. aliases {
  8. serial0 = &uart0;
  9. led-boot = &led_red;
  10. led-failsafe = &led_red;
  11. led-running = &led_blue;
  12. led-upgrade = &led_green;
  13. };
  14. chosen {
  15. bootargs-override = "console=ttyS0,115200n8";
  16. stdout-path = "serial0:115200n8";
  17. };
  18. memory {
  19. reg = <0 0x40000000 0 0x10000000>; // 256mb
  20. };
  21. gpio-keys {
  22. compatible = "gpio-keys";
  23. reset {
  24. label = "reset";
  25. linux,code = <KEY_RESTART>;
  26. gpios = <&pio 1 GPIO_ACTIVE_LOW>;
  27. };
  28. };
  29. leds {
  30. compatible = "gpio-leds";
  31. led_blue: blue {
  32. gpios = <&pio 8 GPIO_ACTIVE_LOW>;
  33. color = <LED_COLOR_ID_BLUE>;
  34. function = LED_FUNCTION_STATUS;
  35. };
  36. led_red: red {
  37. gpios = <&pio 34 GPIO_ACTIVE_LOW>;
  38. color = <LED_COLOR_ID_RED>;
  39. function = LED_FUNCTION_STATUS;
  40. };
  41. led_green: green {
  42. gpios = <&pio 35 GPIO_ACTIVE_LOW>;
  43. color = <LED_COLOR_ID_GREEN>;
  44. function = LED_FUNCTION_STATUS;
  45. };
  46. };
  47. };
  48. &eth {
  49. status = "okay";
  50. gmac0: mac@0 {
  51. /* LAN */
  52. compatible = "mediatek,eth-mac";
  53. reg = <0>;
  54. phy-mode = "2500base-x";
  55. nvmem-cells = <&macaddr_factory_e000 0>;
  56. nvmem-cell-names = "mac-address";
  57. fixed-link {
  58. speed = <2500>;
  59. full-duplex;
  60. pause;
  61. };
  62. };
  63. gmac1: mac@1 {
  64. /* WAN */
  65. compatible = "mediatek,eth-mac";
  66. reg = <1>;
  67. phy-mode = "gmii";
  68. phy-handle = <&int_gbe_phy>;
  69. nvmem-cells = <&macaddr_factory_e000 1>;
  70. nvmem-cell-names = "mac-address";
  71. };
  72. };
  73. &mdio_bus {
  74. switch: switch@1f {
  75. compatible = "mediatek,mt7531";
  76. reg = <31>;
  77. interrupt-controller;
  78. #interrupt-cells = <1>;
  79. interrupt-parent = <&pio>;
  80. interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
  81. reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
  82. };
  83. };
  84. &crypto {
  85. status = "okay";
  86. };
  87. &pio {
  88. spi0_flash_pins: spi0-pins {
  89. mux {
  90. function = "spi";
  91. groups = "spi0", "spi0_wp_hold";
  92. };
  93. conf-pu {
  94. pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
  95. drive-strength = <MTK_DRIVE_8mA>;
  96. bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
  97. };
  98. conf-pd {
  99. pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
  100. drive-strength = <MTK_DRIVE_8mA>;
  101. bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
  102. };
  103. };
  104. };
  105. &spi0 {
  106. pinctrl-names = "default";
  107. pinctrl-0 = <&spi0_flash_pins>;
  108. cs-gpios = <0>, <0>;
  109. #address-cells = <1>;
  110. #size-cells = <0>;
  111. status = "okay";
  112. #address-cells = <1>;
  113. #size-cells = <0>;
  114. spi_nand: spi_nand@0 {
  115. #address-cells = <1>;
  116. #size-cells = <1>;
  117. compatible = "spi-nand";
  118. reg = <1>;
  119. spi-max-frequency = <52000000>;
  120. spi-cal-enable;
  121. spi-cal-mode = "read-data";
  122. spi-cal-datalen = <7>;
  123. spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>;
  124. spi-cal-addrlen = <5>;
  125. spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>;
  126. spi-tx-bus-width = <4>;
  127. spi-rx-bus-width = <4>;
  128. mediatek,nmbm;
  129. mediatek,bmt-max-ratio = <1>;
  130. mediatek,bmt-max-reserved-blocks = <64>;
  131. partitions {
  132. compatible = "fixed-partitions";
  133. #address-cells = <1>;
  134. #size-cells = <1>;
  135. partition@0 {
  136. label = "BL2";
  137. reg = <0x00000 0x0100000>;
  138. read-only;
  139. };
  140. partition@100000 {
  141. label = "u-boot-env";
  142. reg = <0x0100000 0x0080000>;
  143. read-only;
  144. };
  145. factory: partition@180000 {
  146. label = "Factory";
  147. reg = <0x180000 0x0200000>;
  148. read-only;
  149. nvmem-layout {
  150. compatible = "fixed-layout";
  151. #address-cells = <1>;
  152. #size-cells = <1>;
  153. eeprom_factory_0: eeprom@0 {
  154. reg = <0x0 0x1000>;
  155. };
  156. macaddr_factory_e000: macaddr@e000 {
  157. compatible = "mac-base";
  158. reg = <0xe000 0x6>;
  159. #nvmem-cell-cells = <1>;
  160. };
  161. };
  162. };
  163. partition@380000 {
  164. label = "FIP";
  165. reg = <0x380000 0x0200000>;
  166. read-only;
  167. };
  168. partition@580000 {
  169. label = "ubi";
  170. reg = <0x580000 0x4000000>;
  171. compatible = "linux,ubi";
  172. };
  173. };
  174. };
  175. };
  176. &switch {
  177. ports {
  178. #address-cells = <1>;
  179. #size-cells = <0>;
  180. port@0 {
  181. reg = <0>;
  182. label = "lan1";
  183. };
  184. port@6 {
  185. reg = <6>;
  186. label = "cpu";
  187. ethernet = <&gmac0>;
  188. phy-mode = "2500base-x";
  189. fixed-link {
  190. speed = <2500>;
  191. full-duplex;
  192. pause;
  193. };
  194. };
  195. };
  196. };
  197. &uart0 {
  198. status = "okay";
  199. };
  200. &watchdog {
  201. status = "okay";
  202. };
  203. &wifi {
  204. status = "okay";
  205. nvmem-cells = <&eeprom_factory_0>;
  206. nvmem-cell-names = "eeprom";
  207. };