mt7986a-acer-predator-w6.dts 9.5 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /dts-v1/;
  3. #include <dt-bindings/input/input.h>
  4. #include <dt-bindings/gpio/gpio.h>
  5. #include <dt-bindings/leds/common.h>
  6. #include "mt7986a.dtsi"
  7. / {
  8. model = "Acer Predator W6";
  9. compatible = "acer,predator-w6", "mediatek,mt7986a";
  10. aliases {
  11. serial0 = &uart0;
  12. led-boot = &led_status;
  13. led-failsafe = &led_status;
  14. led-running = &led_status;
  15. led-upgrade = &led_status;
  16. };
  17. chosen {
  18. stdout-path = "serial0:115200n8";
  19. bootargs = "dm-mod.create=\"dm-verity,,,ro,0 31544 verity 1 PARTLABEL=rootfs PARTLABEL=rootfs 4096 4096 3943 3944 sha256 2f969fa9e9e4e20b37746f22633e85b178f5db7c143e11f92733a704299cc933 2dd56e34b15c6c84573cf26c4392028421061d2c808975217b45e9a5b49d2087\" rootfstype=squashfs,ext4 rootwait root=/dev/mmcblk0p6 fstools_ignore_partname=1";
  20. };
  21. memory {
  22. reg = <0 0x40000000 0 0x20000000>;
  23. };
  24. reg_1p8v: regulator-1p8v {
  25. compatible = "regulator-fixed";
  26. regulator-name = "fixed-1.8V";
  27. regulator-min-microvolt = <1800000>;
  28. regulator-max-microvolt = <1800000>;
  29. regulator-boot-on;
  30. regulator-always-on;
  31. };
  32. reg_3p3v: regulator-3p3v {
  33. compatible = "regulator-fixed";
  34. regulator-name = "fixed-3.3V";
  35. regulator-min-microvolt = <3300000>;
  36. regulator-max-microvolt = <3300000>;
  37. regulator-boot-on;
  38. regulator-always-on;
  39. };
  40. reg_5v: regulator-5v {
  41. compatible = "regulator-fixed";
  42. regulator-name = "fixed-5V";
  43. regulator-min-microvolt = <5000000>;
  44. regulator-max-microvolt = <5000000>;
  45. regulator-boot-on;
  46. regulator-always-on;
  47. };
  48. gpio-keys {
  49. compatible = "gpio-keys";
  50. factory {
  51. label = "factory";
  52. linux,code = <KEY_RESTART>;
  53. gpios = <&pio 9 GPIO_ACTIVE_LOW>;
  54. };
  55. wps {
  56. label = "wps";
  57. linux,code = <KEY_WPS_BUTTON>;
  58. gpios = <&pio 10 GPIO_ACTIVE_LOW>;
  59. };
  60. };
  61. leds {
  62. compatible = "gpio-leds";
  63. led_status: led@0 {
  64. label = "ant0:red";
  65. gpios = <&pio 1 GPIO_ACTIVE_HIGH>;
  66. default-state = "off";
  67. };
  68. led@1 {
  69. label = "ant0:green";
  70. gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
  71. default-state = "off";
  72. };
  73. led@2 {
  74. label = "ant0:blue";
  75. gpios = <&pio 36 GPIO_ACTIVE_HIGH>;
  76. default-state = "off";
  77. };
  78. led@3 {
  79. label = "ant1:red";
  80. gpios = <&pio 35 GPIO_ACTIVE_HIGH>;
  81. default-state = "off";
  82. };
  83. led@4 {
  84. label = "ant1:green";
  85. gpios = <&pio 34 GPIO_ACTIVE_HIGH>;
  86. default-state = "off";
  87. };
  88. led@5 {
  89. label = "ant1:blue";
  90. gpios = <&pio 33 GPIO_ACTIVE_HIGH>;
  91. default-state = "off";
  92. };
  93. led@6 {
  94. label = "ant2:red";
  95. gpios = <&pio 38 GPIO_ACTIVE_HIGH>;
  96. default-state = "off";
  97. };
  98. led@7 {
  99. label = "ant2:green";
  100. gpios = <&pio 37 GPIO_ACTIVE_HIGH>;
  101. default-state = "off";
  102. };
  103. led@8 {
  104. label = "ant2:blue";
  105. gpios = <&pio 26 GPIO_ACTIVE_HIGH>;
  106. default-state = "off";
  107. };
  108. led@9 {
  109. label = "ant3:red";
  110. gpios = <&pio 25 GPIO_ACTIVE_HIGH>;
  111. default-state = "off";
  112. };
  113. led@10 {
  114. label = "ant3:green";
  115. gpios = <&pio 24 GPIO_ACTIVE_HIGH>;
  116. default-state = "off";
  117. };
  118. led@11 {
  119. label = "ant3:blue";
  120. gpios = <&pio 23 GPIO_ACTIVE_HIGH>;
  121. default-state = "off";
  122. };
  123. led@12 {
  124. label = "ant4:red";
  125. gpios = <&pio 28 GPIO_ACTIVE_HIGH>;
  126. default-state = "off";
  127. };
  128. led@13 {
  129. label = "ant4:green";
  130. gpios = <&pio 27 GPIO_ACTIVE_HIGH>;
  131. default-state = "off";
  132. };
  133. led@14 {
  134. label = "ant4:blue";
  135. gpios = <&pio 32 GPIO_ACTIVE_HIGH>;
  136. default-state = "off";
  137. };
  138. led@15 {
  139. label = "ant5:red";
  140. gpios = <&pio 45 GPIO_ACTIVE_HIGH>;
  141. default-state = "off";
  142. };
  143. led@16 {
  144. label = "ant5:green";
  145. gpios = <&pio 44 GPIO_ACTIVE_HIGH>;
  146. default-state = "off";
  147. };
  148. led@17 {
  149. label = "ant5:blue";
  150. gpios = <&pio 43 GPIO_ACTIVE_HIGH>;
  151. default-state = "off";
  152. };
  153. };
  154. };
  155. &eth {
  156. status = "okay";
  157. gmac0: mac@0 {
  158. /* LAN */
  159. compatible = "mediatek,eth-mac";
  160. reg = <0>;
  161. phy-mode = "2500base-x";
  162. fixed-link {
  163. speed = <2500>;
  164. full-duplex;
  165. pause;
  166. };
  167. };
  168. gmac1: mac@1 {
  169. /* WAN */
  170. compatible = "mediatek,eth-mac";
  171. reg = <1>;
  172. phy-mode = "2500base-x";
  173. phy-handle = <&phy6>;
  174. };
  175. mdio: mdio-bus {
  176. #address-cells = <1>;
  177. #size-cells = <0>;
  178. };
  179. };
  180. &mdio {
  181. phy6: phy@6 {
  182. compatible = "ethernet-phy-ieee802.3-c45";
  183. reg = <6>;
  184. reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
  185. reset-assert-us = <10000>;
  186. reset-deassert-us = <10000>;
  187. /* LED0: nc ; LED1: nc ; LED2: Amber ; LED3: Green */
  188. mxl,led-config = <0x0 0x0 0x370 0x80>;
  189. };
  190. switch: switch@1f {
  191. compatible = "mediatek,mt7531";
  192. reg = <31>;
  193. reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
  194. reset-assert-us = <10000>;
  195. reset-deassert-us = <10000>;
  196. };
  197. };
  198. &pio {
  199. mmc0_pins_default: mmc0-pins {
  200. mux {
  201. function = "emmc";
  202. groups = "emmc_51";
  203. };
  204. conf-cmd-dat {
  205. pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
  206. "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
  207. "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
  208. input-enable;
  209. drive-strength = <4>;
  210. mediatek,pull-up-adv = <1>; /* pull-up 10K */
  211. };
  212. conf-clk {
  213. pins = "EMMC_CK";
  214. drive-strength = <6>;
  215. mediatek,pull-down-adv = <2>; /* pull-down 50K */
  216. };
  217. conf-ds {
  218. pins = "EMMC_DSL";
  219. mediatek,pull-down-adv = <2>; /* pull-down 50K */
  220. };
  221. conf-rst {
  222. pins = "EMMC_RSTB";
  223. drive-strength = <4>;
  224. mediatek,pull-up-adv = <1>; /* pull-up 10K */
  225. };
  226. };
  227. mmc0_pins_uhs: mmc0-uhs-pins {
  228. mux {
  229. function = "emmc";
  230. groups = "emmc_51";
  231. };
  232. conf-cmd-dat {
  233. pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
  234. "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
  235. "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
  236. input-enable;
  237. drive-strength = <4>;
  238. mediatek,pull-up-adv = <1>; /* pull-up 10K */
  239. };
  240. conf-clk {
  241. pins = "EMMC_CK";
  242. drive-strength = <6>;
  243. mediatek,pull-down-adv = <2>; /* pull-down 50K */
  244. };
  245. conf-ds {
  246. pins = "EMMC_DSL";
  247. mediatek,pull-down-adv = <2>; /* pull-down 50K */
  248. };
  249. conf-rst {
  250. pins = "EMMC_RSTB";
  251. drive-strength = <4>;
  252. mediatek,pull-up-adv = <1>; /* pull-up 10K */
  253. };
  254. };
  255. pcie_pins: pcie-pins {
  256. mux {
  257. function = "pcie";
  258. groups = "pcie_pereset";
  259. };
  260. };
  261. wf_2g_5g_pins: wf_2g_5g-pins {
  262. mux {
  263. function = "wifi";
  264. groups = "wf_2g", "wf_5g";
  265. };
  266. conf {
  267. pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
  268. "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
  269. "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
  270. "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
  271. "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
  272. "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
  273. "WF1_TOP_CLK", "WF1_TOP_DATA";
  274. drive-strength = <4>;
  275. };
  276. };
  277. wf_dbdc_pins: wf-dbdc-pins {
  278. mux {
  279. function = "wifi";
  280. groups = "wf_dbdc";
  281. };
  282. conf {
  283. pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
  284. "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
  285. "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
  286. "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
  287. "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
  288. "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
  289. "WF1_TOP_CLK", "WF1_TOP_DATA";
  290. drive-strength = <4>;
  291. };
  292. };
  293. };
  294. &switch {
  295. ports {
  296. #address-cells = <1>;
  297. #size-cells = <0>;
  298. port@0 {
  299. reg = <0>;
  300. label = "game";
  301. };
  302. port@1 {
  303. reg = <1>;
  304. label = "lan1";
  305. };
  306. port@2 {
  307. reg = <2>;
  308. label = "lan2";
  309. };
  310. port@3 {
  311. reg = <3>;
  312. label = "lan3";
  313. };
  314. port@6 {
  315. reg = <6>;
  316. label = "cpu";
  317. ethernet = <&gmac0>;
  318. phy-mode = "2500base-x";
  319. fixed-link {
  320. speed = <2500>;
  321. full-duplex;
  322. pause;
  323. };
  324. };
  325. };
  326. mdio {
  327. #address-cells = <1>;
  328. #size-cells = <0>;
  329. phy@0 {
  330. reg = <0>;
  331. mediatek,led-config = <
  332. 0x21 0x8009 /* BASIC_CTRL */
  333. 0x22 0x0c00 /* ON_DURATION */
  334. 0x23 0x1400 /* BLINK_DURATION */
  335. 0x24 0xc001 /* LED0_ON_CTRL */
  336. 0x25 0x0000 /* LED0_BLINK_CTRL */
  337. 0x26 0xc007 /* LED1_ON_CTRL */
  338. 0x27 0x003f /* LED1_BLINK_CTRL */
  339. >;
  340. };
  341. phy@1 {
  342. reg = <1>;
  343. mediatek,led-config = <
  344. 0x21 0x8009 /* BASIC_CTRL */
  345. 0x22 0x0c00 /* ON_DURATION */
  346. 0x23 0x1400 /* BLINK_DURATION */
  347. 0x24 0xc001 /* LED0_ON_CTRL */
  348. 0x25 0x0000 /* LED0_BLINK_CTRL */
  349. 0x26 0xc007 /* LED1_ON_CTRL */
  350. 0x27 0x003f /* LED1_BLINK_CTRL */
  351. >;
  352. };
  353. phy@2 {
  354. reg = <2>;
  355. mediatek,led-config = <
  356. 0x21 0x8009 /* BASIC_CTRL */
  357. 0x22 0x0c00 /* ON_DURATION */
  358. 0x23 0x1400 /* BLINK_DURATION */
  359. 0x24 0xc001 /* LED0_ON_CTRL */
  360. 0x25 0x0000 /* LED0_BLINK_CTRL */
  361. 0x26 0xc007 /* LED1_ON_CTRL */
  362. 0x27 0x003f /* LED1_BLINK_CTRL */
  363. >;
  364. };
  365. phy@3 {
  366. reg = <3>;
  367. mediatek,led-config = <
  368. 0x21 0x8009 /* BASIC_CTRL */
  369. 0x22 0x0c00 /* ON_DURATION */
  370. 0x23 0x1400 /* BLINK_DURATION */
  371. 0x24 0xc001 /* LED0_ON_CTRL */
  372. 0x25 0x0000 /* LED0_BLINK_CTRL */
  373. 0x26 0xc007 /* LED1_ON_CTRL */
  374. 0x27 0x003f /* LED1_BLINK_CTRL */
  375. >;
  376. };
  377. };
  378. };
  379. &wifi {
  380. status = "okay";
  381. pinctrl-names = "default", "dbdc";
  382. pinctrl-0 = <&wf_2g_5g_pins>;
  383. pinctrl-1 = <&wf_dbdc_pins>;
  384. };
  385. &trng {
  386. status = "okay";
  387. };
  388. &watchdog {
  389. status = "okay";
  390. };
  391. &crypto {
  392. status = "okay";
  393. };
  394. &uart0 {
  395. status = "okay";
  396. };
  397. &ssusb {
  398. vusb33-supply = <&reg_3p3v>;
  399. vbus-supply = <&reg_5v>;
  400. status = "okay";
  401. };
  402. &usb_phy {
  403. status = "okay";
  404. };
  405. &mmc0 {
  406. status = "okay";
  407. pinctrl-names = "default", "state_uhs";
  408. pinctrl-0 = <&mmc0_pins_default>;
  409. pinctrl-1 = <&mmc0_pins_uhs>;
  410. bus-width = <0x08>;
  411. max-frequency = <200000000>;
  412. cap-mmc-highspeed;
  413. mmc-hs200-1_8v;
  414. mmc-hs400-1_8v;
  415. hs400-ds-delay = <0x14014>;
  416. vmmc-supply = <&reg_3p3v>;
  417. vqmmc-supply = <&reg_1p8v>;
  418. non-removable;
  419. no-sd;
  420. no-sdio;
  421. };
  422. &pcie {
  423. pinctrl-names = "default";
  424. pinctrl-0 = <&pcie_pins>;
  425. status = "okay";
  426. };
  427. &pcie_phy {
  428. status = "okay";
  429. };