mt7986a-xiaomi-redmi-router-ax6000.dtsi 4.7 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /dts-v1/;
  3. #include <dt-bindings/input/input.h>
  4. #include <dt-bindings/gpio/gpio.h>
  5. #include <dt-bindings/leds/common.h>
  6. #include "mt7986a.dtsi"
  7. / {
  8. aliases {
  9. serial0 = &uart0;
  10. led-boot = &led_status_rgb;
  11. led-failsafe = &led_status_rgb;
  12. led-running = &led_status_rgb;
  13. led-upgrade = &led_status_rgb;
  14. };
  15. chosen: chosen {
  16. stdout-path = "serial0:115200n8";
  17. };
  18. memory {
  19. reg = <0 0x40000000 0 0x20000000>;
  20. };
  21. keys {
  22. compatible = "gpio-keys";
  23. reset {
  24. label = "reset";
  25. gpios = <&pio 9 GPIO_ACTIVE_LOW>;
  26. linux,code = <KEY_RESTART>;
  27. };
  28. mesh {
  29. label = "mesh";
  30. gpios = <&pio 10 GPIO_ACTIVE_LOW>;
  31. linux,code = <BTN_9>;
  32. linux,input-type = <EV_SW>;
  33. };
  34. };
  35. };
  36. &crypto {
  37. status = "okay";
  38. };
  39. &eth {
  40. status = "okay";
  41. gmac0: mac@0 {
  42. compatible = "mediatek,eth-mac";
  43. reg = <0>;
  44. phy-mode = "2500base-x";
  45. nvmem-cells = <&macaddr_factory_4 (-1)>;
  46. nvmem-cell-names = "mac-address";
  47. fixed-link {
  48. speed = <2500>;
  49. full-duplex;
  50. pause;
  51. };
  52. };
  53. mdio: mdio-bus {
  54. #address-cells = <1>;
  55. #size-cells = <0>;
  56. };
  57. };
  58. &mdio {
  59. switch: switch@1f {
  60. compatible = "mediatek,mt7531";
  61. reg = <31>;
  62. reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
  63. interrupt-controller;
  64. #interrupt-cells = <1>;
  65. interrupt-parent = <&pio>;
  66. interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
  67. };
  68. };
  69. &pio {
  70. spi_flash_pins: spi-flash-pins-33-to-38 {
  71. mux {
  72. function = "spi";
  73. groups = "spi0", "spi0_wp_hold";
  74. };
  75. conf-pu {
  76. pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
  77. drive-strength = <8>;
  78. mediatek,pull-up-adv = <0>; /* bias-disable */
  79. };
  80. conf-pd {
  81. pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
  82. drive-strength = <8>;
  83. mediatek,pull-down-adv = <0>; /* bias-disable */
  84. };
  85. };
  86. spi_led_pins: spic-pins-29-to-32 {
  87. mux {
  88. function = "spi";
  89. groups = "spi1_2";
  90. };
  91. };
  92. wf_2g_5g_pins: wf_2g_5g-pins {
  93. mux {
  94. function = "wifi";
  95. groups = "wf_2g", "wf_5g";
  96. };
  97. conf {
  98. pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
  99. "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
  100. "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
  101. "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
  102. "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
  103. "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
  104. "WF1_TOP_CLK", "WF1_TOP_DATA";
  105. drive-strength = <4>;
  106. };
  107. };
  108. };
  109. &spi0 {
  110. pinctrl-names = "default";
  111. pinctrl-0 = <&spi_flash_pins>;
  112. status = "okay";
  113. spi_nand_flash: flash@0 {
  114. compatible = "spi-nand";
  115. #address-cells = <1>;
  116. #size-cells = <1>;
  117. reg = <0>;
  118. spi-max-frequency = <20000000>;
  119. spi-tx-bus-width = <4>;
  120. spi-rx-bus-width = <4>;
  121. partitions: partitions {
  122. compatible = "fixed-partitions";
  123. #address-cells = <1>;
  124. #size-cells = <1>;
  125. partition@0 {
  126. label = "BL2";
  127. reg = <0x0 0x100000>;
  128. read-only;
  129. };
  130. partition@100000 {
  131. label = "Nvram";
  132. reg = <0x100000 0x40000>;
  133. };
  134. partition@140000 {
  135. label = "Bdata";
  136. reg = <0x140000 0x40000>;
  137. };
  138. factory: partition@180000 {
  139. label = "Factory";
  140. reg = <0x180000 0x200000>;
  141. read-only;
  142. nvmem-layout {
  143. compatible = "fixed-layout";
  144. #address-cells = <1>;
  145. #size-cells = <1>;
  146. macaddr_factory_4: macaddr@4 {
  147. compatible = "mac-base";
  148. reg = <0x4 0x6>;
  149. #nvmem-cell-cells = <1>;
  150. };
  151. };
  152. };
  153. partition@380000 {
  154. label = "FIP";
  155. reg = <0x380000 0x200000>;
  156. read-only;
  157. };
  158. };
  159. };
  160. };
  161. &spi1 {
  162. pinctrl-names = "default";
  163. pinctrl-0 = <&spi_led_pins>;
  164. status = "okay";
  165. ws2812b@0 {
  166. #address-cells = <1>;
  167. #size-cells = <0>;
  168. compatible = "worldsemi,ws2812b";
  169. reg = <0>;
  170. spi-max-frequency = <3000000>;
  171. led_status_rgb: led@0 {
  172. reg = <0>;
  173. function = LED_FUNCTION_STATUS;
  174. color = <LED_COLOR_ID_RGB>;
  175. color-index = <LED_COLOR_ID_RED LED_COLOR_ID_GREEN LED_COLOR_ID_BLUE>;
  176. };
  177. led_network_rgb: led@1 {
  178. reg = <1>;
  179. /* Hardcoding here for backward compatibility */
  180. function = "network";
  181. color = <LED_COLOR_ID_RGB>;
  182. color-index = <LED_COLOR_ID_RED LED_COLOR_ID_GREEN LED_COLOR_ID_BLUE>;
  183. };
  184. };
  185. };
  186. &switch {
  187. ports {
  188. #address-cells = <1>;
  189. #size-cells = <0>;
  190. port@1 {
  191. reg = <1>;
  192. label = "lan4";
  193. };
  194. port@2 {
  195. reg = <2>;
  196. label = "lan3";
  197. };
  198. port@3 {
  199. reg = <3>;
  200. label = "lan2";
  201. };
  202. port@4 {
  203. reg = <4>;
  204. label = "wan";
  205. };
  206. port@6 {
  207. reg = <6>;
  208. ethernet = <&gmac0>;
  209. phy-mode = "2500base-x";
  210. fixed-link {
  211. speed = <2500>;
  212. full-duplex;
  213. pause;
  214. };
  215. };
  216. };
  217. };
  218. &trng {
  219. status = "okay";
  220. };
  221. &uart0 {
  222. status = "okay";
  223. };
  224. &watchdog {
  225. status = "okay";
  226. };
  227. &wifi {
  228. status = "okay";
  229. pinctrl-names = "default";
  230. pinctrl-0 = <&wf_2g_5g_pins>;
  231. mediatek,mtd-eeprom = <&factory 0x0>;
  232. };
  233. &uart0 {
  234. status = "okay";
  235. };