mt7986b-netgear-wax220.dts 5.4 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /dts-v1/;
  3. #include <dt-bindings/input/input.h>
  4. #include <dt-bindings/gpio/gpio.h>
  5. #include <dt-bindings/leds/common.h>
  6. #include "mt7986b.dtsi"
  7. / {
  8. model = "Netgear WAX220";
  9. compatible = "netgear,wax220", "mediatek,mt7986b";
  10. aliases {
  11. serial0 = &uart0;
  12. led-boot = &led_power_blue;
  13. led-failsafe = &led_power_amber;
  14. led-running = &led_power_green;
  15. led-upgrade = &led_power_amber;
  16. };
  17. gpio-keys {
  18. compatible = "gpio-keys";
  19. reset {
  20. gpios = <&pio 9 GPIO_ACTIVE_LOW>;
  21. linux,code = <KEY_RESTART>;
  22. label = "reset";
  23. };
  24. };
  25. chosen {
  26. stdout-path = "serial0:115200n8";
  27. };
  28. leds {
  29. compatible = "gpio-leds";
  30. wlan5g_green {
  31. gpios = <&pio 12 GPIO_ACTIVE_LOW>;
  32. label = "green:wlan5g";
  33. };
  34. led_power_amber: power_amber {
  35. gpios = <&pio 15 GPIO_ACTIVE_LOW>;
  36. function = LED_FUNCTION_POWER;
  37. color = <LED_COLOR_ID_AMBER>;
  38. };
  39. wlan2g_green {
  40. gpios = <&pio 19 GPIO_ACTIVE_HIGH>;
  41. label = "green:wlan2g";
  42. };
  43. led_power_blue: power_blue {
  44. gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
  45. function = LED_FUNCTION_POWER;
  46. color = <LED_COLOR_ID_BLUE>;
  47. };
  48. led_power_green: power_green {
  49. gpios = <&pio 10 GPIO_ACTIVE_LOW>;
  50. function = LED_FUNCTION_POWER;
  51. color = <LED_COLOR_ID_GREEN>;
  52. };
  53. wlan2g_blue {
  54. gpios = <&pio 1 GPIO_ACTIVE_LOW>;
  55. label = "blue:wlan2g";
  56. };
  57. lan_green {
  58. gpios = <&pio 22 GPIO_ACTIVE_HIGH>;
  59. function = LED_FUNCTION_LAN;
  60. color = <LED_COLOR_ID_GREEN>;
  61. };
  62. lan_amber {
  63. gpios = <&pio 13 GPIO_ACTIVE_LOW>;
  64. function = LED_FUNCTION_LAN;
  65. color = <LED_COLOR_ID_AMBER>;
  66. };
  67. wlan5g_blue {
  68. gpios = <&pio 2 GPIO_ACTIVE_LOW>;
  69. label = "blue:wlan5g";
  70. };
  71. };
  72. };
  73. &crypto {
  74. status = "okay";
  75. };
  76. &eth {
  77. status = "okay";
  78. gmac1: mac@1 {
  79. compatible = "mediatek,eth-mac";
  80. reg = <1>;
  81. phy-handle = <&phy6>;
  82. phy-mode = "2500base-x";
  83. };
  84. mdio: mdio-bus {
  85. #address-cells = <1>;
  86. #size-cells = <0>;
  87. };
  88. };
  89. &mdio {
  90. phy6: ethernet-phy@6 {
  91. reg = <6>;
  92. reset-assert-us = <100000>;
  93. reset-deassert-us = <100000>;
  94. reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
  95. interrupt-controller;
  96. #interrupt-cells = <1>;
  97. interrupt-parent = <&pio>;
  98. interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
  99. };
  100. };
  101. &pio {
  102. spi_flash_pins: spi-flash-pins-33-to-38 {
  103. mux {
  104. function = "spi";
  105. groups = "spi0", "spi0_wp_hold";
  106. };
  107. conf-pu {
  108. pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
  109. drive-strength = <8>;
  110. mediatek,pull-up-adv = <0>; /* bias-disable */
  111. };
  112. conf-pd {
  113. pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
  114. drive-strength = <8>;
  115. mediatek,pull-down-adv = <0>; /* bias-disable */
  116. };
  117. };
  118. wf_2g_5g_pins: wf_2g_5g-pins {
  119. mux {
  120. function = "wifi";
  121. groups = "wf_2g", "wf_5g";
  122. };
  123. conf {
  124. pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
  125. "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
  126. "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
  127. "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
  128. "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
  129. "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
  130. "WF1_TOP_CLK", "WF1_TOP_DATA";
  131. drive-strength = <4>;
  132. };
  133. };
  134. wf_dbdc_pins: wf-dbdc-pins {
  135. mux {
  136. function = "wifi";
  137. groups = "wf_dbdc";
  138. };
  139. conf {
  140. pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
  141. "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
  142. "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
  143. "WF0_TOP_CLK", "WF0_TOP_DATA";
  144. drive-strength = <4>;
  145. };
  146. };
  147. };
  148. &spi0 {
  149. pinctrl-names = "default";
  150. pinctrl-0 = <&spi_flash_pins>;
  151. status = "okay";
  152. spi_nand_flash: flash@0 {
  153. #address-cells = <1>;
  154. #size-cells = <1>;
  155. compatible = "spi-nand";
  156. reg = <0>;
  157. spi-max-frequency = <20000000>;
  158. spi-tx-bus-width = <4>;
  159. spi-rx-bus-width = <4>;
  160. mediatek,nmbm;
  161. mediatek,bmt-max-ratio = <1>;
  162. mediatek,bmt-max-reserved-blocks = <256>;
  163. mediatek,bmt-remap-range = <0x0 0x580000>;
  164. partitions: partitions {
  165. #address-cells = <0x1>;
  166. #size-cells = <0x1>;
  167. compatible = "fixed-partitions";
  168. partition@0 {
  169. label = "BL2";
  170. read-only;
  171. reg = <0x0 0x100000>;
  172. };
  173. partition@100000 {
  174. label = "u-boot-env";
  175. reg = <0x100000 0x80000>;
  176. };
  177. factory: partition@180000 {
  178. label = "Factory";
  179. reg = <0x180000 0x200000>;
  180. };
  181. partition@380000 {
  182. label = "FIP";
  183. reg = <0x380000 0x200000>;
  184. };
  185. partition@580000 {
  186. label = "ubi";
  187. reg = <0x580000 0x5140000>;
  188. };
  189. partition@56c0000 {
  190. label = "RAE";
  191. reg = <0x56c0000 0x400000>;
  192. };
  193. partition@5ac0000 {
  194. label = "POT";
  195. reg = <0x5ac0000 0x100000>;
  196. };
  197. partition@5bc0000 {
  198. label = "Language";
  199. reg = <0x5bc0000 0x400000>;
  200. };
  201. partition@5fc0000 {
  202. label = "Traffic";
  203. reg = <0x5fc0000 0x200000>;
  204. };
  205. partition@61c0000 {
  206. label = "Cert";
  207. reg = <0x61c0000 0x100000>;
  208. };
  209. partition@62c0000 {
  210. label = "NTGRcryptK";
  211. reg = <0x62c0000 0x100000>;
  212. };
  213. partition@63c0000 {
  214. label = "NTGRcryptD";
  215. reg = <0x63c0000 0x500000>;
  216. };
  217. partition@68c0000 {
  218. label = "LOG";
  219. reg = <0x68c0000 0x100000>;
  220. };
  221. partition@69c0000 {
  222. label = "User_data";
  223. reg = <0x69c0000 0x640000>;
  224. };
  225. };
  226. };
  227. };
  228. &trng {
  229. status = "okay";
  230. };
  231. &uart0 {
  232. status = "okay";
  233. };
  234. &watchdog {
  235. status = "okay";
  236. };
  237. &wifi {
  238. status = "okay";
  239. pinctrl-names = "default", "dbdc";
  240. pinctrl-0 = <&wf_2g_5g_pins>;
  241. pinctrl-1 = <&wf_dbdc_pins>;
  242. mediatek,mtd-eeprom = <&factory 0x0>;
  243. };