010-v6.3-arm64-dts-mt7986-add-Bananapi-R3.patch 15 KB

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  1. From a751f7412e0098801673b80bc7a4738ae7d710ce Mon Sep 17 00:00:00 2001
  2. From: Frank Wunderlich <[email protected]>
  3. Date: Fri, 6 Jan 2023 16:28:45 +0100
  4. Subject: [PATCH 10/19] arm64: dts: mt7986: add Bananapi R3
  5. Add support for Bananapi R3 SBC.
  6. - SD/eMMC support (switching first 4 bits of data-bus with sw6/D)
  7. - SPI-NAND/NOR support (switched CS by sw5/C)
  8. - all rj45 ports and both SFP working (eth1/lan4)
  9. - all USB-Ports + SIM-Slot tested
  10. - i2c and all uarts tested
  11. - wifi tested (with eeprom calibration data)
  12. The device can boot from all 4 storage options. Both, SPI and MMC, can
  13. be switched using hardware switches on the board, see
  14. https://wiki.banana-pi.org/Banana_Pi_BPI-R3#Jumper_setting
  15. Signed-off-by: Frank Wunderlich <[email protected]>
  16. Link: https://lore.kernel.org/r/[email protected]
  17. Signed-off-by: Matthias Brugger <[email protected]>
  18. ---
  19. arch/arm64/boot/dts/mediatek/Makefile | 5 +
  20. .../mt7986a-bananapi-bpi-r3-emmc.dtso | 29 ++
  21. .../mt7986a-bananapi-bpi-r3-nand.dtso | 55 +++
  22. .../mediatek/mt7986a-bananapi-bpi-r3-nor.dtso | 68 +++
  23. .../mediatek/mt7986a-bananapi-bpi-r3-sd.dtso | 23 +
  24. .../dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 450 ++++++++++++++++++
  25. 6 files changed, 630 insertions(+)
  26. create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
  27. create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
  28. create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
  29. create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
  30. create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
  31. --- a/arch/arm64/boot/dts/mediatek/Makefile
  32. +++ b/arch/arm64/boot/dts/mediatek/Makefile
  33. @@ -7,6 +7,11 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-ev
  34. dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
  35. dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
  36. dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
  37. +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3.dtb
  38. +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtbo
  39. +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo
  40. +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo
  41. +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo
  42. dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb
  43. dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb
  44. dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb
  45. --- /dev/null
  46. +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
  47. @@ -0,0 +1,29 @@
  48. +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
  49. +/*
  50. + * Copyright (C) 2021 MediaTek Inc.
  51. + * Author: Sam.Shih <[email protected]>
  52. + */
  53. +
  54. +/dts-v1/;
  55. +/plugin/;
  56. +
  57. +/ {
  58. + compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
  59. +
  60. + fragment@0 {
  61. + target-path = "/soc/mmc@11230000";
  62. + __overlay__ {
  63. + bus-width = <8>;
  64. + max-frequency = <200000000>;
  65. + cap-mmc-highspeed;
  66. + mmc-hs200-1_8v;
  67. + mmc-hs400-1_8v;
  68. + hs400-ds-delay = <0x14014>;
  69. + non-removable;
  70. + no-sd;
  71. + no-sdio;
  72. + status = "okay";
  73. + };
  74. + };
  75. +};
  76. +
  77. --- /dev/null
  78. +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
  79. @@ -0,0 +1,55 @@
  80. +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
  81. +/*
  82. + * Authors: Daniel Golle <[email protected]>
  83. + * Frank Wunderlich <[email protected]>
  84. + */
  85. +
  86. +/dts-v1/;
  87. +/plugin/;
  88. +
  89. +/ {
  90. + compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
  91. +
  92. + fragment@0 {
  93. + target-path = "/soc/spi@1100a000";
  94. + __overlay__ {
  95. + #address-cells = <1>;
  96. + #size-cells = <0>;
  97. + spi_nand: spi_nand@0 {
  98. + compatible = "spi-nand";
  99. + reg = <0>;
  100. + spi-max-frequency = <10000000>;
  101. + spi-tx-bus-width = <4>;
  102. + spi-rx-bus-width = <4>;
  103. +
  104. + partitions {
  105. + compatible = "fixed-partitions";
  106. + #address-cells = <1>;
  107. + #size-cells = <1>;
  108. +
  109. + partition@0 {
  110. + label = "bl2";
  111. + reg = <0x0 0x80000>;
  112. + read-only;
  113. + };
  114. +
  115. + partition@80000 {
  116. + label = "reserved";
  117. + reg = <0x80000 0x300000>;
  118. + };
  119. +
  120. + partition@380000 {
  121. + label = "fip";
  122. + reg = <0x380000 0x200000>;
  123. + read-only;
  124. + };
  125. +
  126. + partition@580000 {
  127. + label = "ubi";
  128. + reg = <0x580000 0x7a80000>;
  129. + };
  130. + };
  131. + };
  132. + };
  133. + };
  134. +};
  135. --- /dev/null
  136. +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
  137. @@ -0,0 +1,68 @@
  138. +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
  139. +/*
  140. + * Authors: Daniel Golle <[email protected]>
  141. + * Frank Wunderlich <[email protected]>
  142. + */
  143. +
  144. +/dts-v1/;
  145. +/plugin/;
  146. +
  147. +/ {
  148. + compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
  149. +
  150. + fragment@0 {
  151. + target-path = "/soc/spi@1100a000";
  152. + __overlay__ {
  153. + #address-cells = <1>;
  154. + #size-cells = <0>;
  155. + flash@0 {
  156. + compatible = "jedec,spi-nor";
  157. + reg = <0>;
  158. + spi-max-frequency = <10000000>;
  159. +
  160. + partitions {
  161. + compatible = "fixed-partitions";
  162. + #address-cells = <1>;
  163. + #size-cells = <1>;
  164. +
  165. + partition@0 {
  166. + label = "bl2";
  167. + reg = <0x0 0x20000>;
  168. + read-only;
  169. + };
  170. +
  171. + partition@20000 {
  172. + label = "reserved";
  173. + reg = <0x20000 0x20000>;
  174. + };
  175. +
  176. + partition@40000 {
  177. + label = "u-boot-env";
  178. + reg = <0x40000 0x40000>;
  179. + };
  180. +
  181. + partition@80000 {
  182. + label = "reserved2";
  183. + reg = <0x80000 0x80000>;
  184. + };
  185. +
  186. + partition@100000 {
  187. + label = "fip";
  188. + reg = <0x100000 0x80000>;
  189. + read-only;
  190. + };
  191. +
  192. + partition@180000 {
  193. + label = "recovery";
  194. + reg = <0x180000 0xa80000>;
  195. + };
  196. +
  197. + partition@c00000 {
  198. + label = "fit";
  199. + reg = <0xc00000 0x1400000>;
  200. + };
  201. + };
  202. + };
  203. + };
  204. + };
  205. +};
  206. --- /dev/null
  207. +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
  208. @@ -0,0 +1,23 @@
  209. +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
  210. +/*
  211. + * Copyright (C) 2021 MediaTek Inc.
  212. + * Author: Sam.Shih <[email protected]>
  213. + */
  214. +
  215. +/dts-v1/;
  216. +/plugin/;
  217. +
  218. +/ {
  219. + compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
  220. +
  221. + fragment@0 {
  222. + target-path = "/soc/mmc@11230000";
  223. + __overlay__ {
  224. + bus-width = <4>;
  225. + max-frequency = <52000000>;
  226. + cap-sd-highspeed;
  227. + status = "okay";
  228. + };
  229. + };
  230. +};
  231. +
  232. --- /dev/null
  233. +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
  234. @@ -0,0 +1,450 @@
  235. +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
  236. +/*
  237. + * Copyright (C) 2021 MediaTek Inc.
  238. + * Authors: Sam.Shih <[email protected]>
  239. + * Frank Wunderlich <[email protected]>
  240. + * Daniel Golle <[email protected]>
  241. + */
  242. +
  243. +/dts-v1/;
  244. +#include <dt-bindings/gpio/gpio.h>
  245. +#include <dt-bindings/input/input.h>
  246. +#include <dt-bindings/leds/common.h>
  247. +#include <dt-bindings/pinctrl/mt65xx.h>
  248. +
  249. +#include "mt7986a.dtsi"
  250. +
  251. +/ {
  252. + model = "Bananapi BPI-R3";
  253. + compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
  254. +
  255. + aliases {
  256. + serial0 = &uart0;
  257. + ethernet0 = &gmac0;
  258. + ethernet1 = &gmac1;
  259. + };
  260. +
  261. + chosen {
  262. + stdout-path = "serial0:115200n8";
  263. + };
  264. +
  265. + dcin: regulator-12vd {
  266. + compatible = "regulator-fixed";
  267. + regulator-name = "12vd";
  268. + regulator-min-microvolt = <12000000>;
  269. + regulator-max-microvolt = <12000000>;
  270. + regulator-boot-on;
  271. + regulator-always-on;
  272. + };
  273. +
  274. + gpio-keys {
  275. + compatible = "gpio-keys";
  276. +
  277. + reset-key {
  278. + label = "reset";
  279. + linux,code = <KEY_RESTART>;
  280. + gpios = <&pio 9 GPIO_ACTIVE_LOW>;
  281. + };
  282. +
  283. + wps-key {
  284. + label = "wps";
  285. + linux,code = <KEY_WPS_BUTTON>;
  286. + gpios = <&pio 10 GPIO_ACTIVE_LOW>;
  287. + };
  288. + };
  289. +
  290. + /* i2c of the left SFP cage (wan) */
  291. + i2c_sfp1: i2c-gpio-0 {
  292. + compatible = "i2c-gpio";
  293. + sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  294. + scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  295. + i2c-gpio,delay-us = <2>;
  296. + #address-cells = <1>;
  297. + #size-cells = <0>;
  298. + };
  299. +
  300. + /* i2c of the right SFP cage (lan) */
  301. + i2c_sfp2: i2c-gpio-1 {
  302. + compatible = "i2c-gpio";
  303. + sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  304. + scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  305. + i2c-gpio,delay-us = <2>;
  306. + #address-cells = <1>;
  307. + #size-cells = <0>;
  308. + };
  309. +
  310. + leds {
  311. + compatible = "gpio-leds";
  312. +
  313. + green_led: led-0 {
  314. + color = <LED_COLOR_ID_GREEN>;
  315. + function = LED_FUNCTION_POWER;
  316. + gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
  317. + default-state = "on";
  318. + };
  319. +
  320. + blue_led: led-1 {
  321. + color = <LED_COLOR_ID_BLUE>;
  322. + function = LED_FUNCTION_STATUS;
  323. + gpios = <&pio 86 GPIO_ACTIVE_HIGH>;
  324. + default-state = "off";
  325. + };
  326. + };
  327. +
  328. + reg_1p8v: regulator-1p8v {
  329. + compatible = "regulator-fixed";
  330. + regulator-name = "1.8vd";
  331. + regulator-min-microvolt = <1800000>;
  332. + regulator-max-microvolt = <1800000>;
  333. + regulator-boot-on;
  334. + regulator-always-on;
  335. + vin-supply = <&dcin>;
  336. + };
  337. +
  338. + reg_3p3v: regulator-3p3v {
  339. + compatible = "regulator-fixed";
  340. + regulator-name = "3.3vd";
  341. + regulator-min-microvolt = <3300000>;
  342. + regulator-max-microvolt = <3300000>;
  343. + regulator-boot-on;
  344. + regulator-always-on;
  345. + vin-supply = <&dcin>;
  346. + };
  347. +
  348. + /* left SFP cage (wan) */
  349. + sfp1: sfp-1 {
  350. + compatible = "sff,sfp";
  351. + i2c-bus = <&i2c_sfp1>;
  352. + los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
  353. + mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
  354. + tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
  355. + tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
  356. + };
  357. +
  358. + /* right SFP cage (lan) */
  359. + sfp2: sfp-2 {
  360. + compatible = "sff,sfp";
  361. + i2c-bus = <&i2c_sfp2>;
  362. + los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
  363. + mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
  364. + tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
  365. + tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
  366. + };
  367. +};
  368. +
  369. +&crypto {
  370. + status = "okay";
  371. +};
  372. +
  373. +&eth {
  374. + status = "okay";
  375. +
  376. + gmac0: mac@0 {
  377. + compatible = "mediatek,eth-mac";
  378. + reg = <0>;
  379. + phy-mode = "2500base-x";
  380. +
  381. + fixed-link {
  382. + speed = <2500>;
  383. + full-duplex;
  384. + pause;
  385. + };
  386. + };
  387. +
  388. + gmac1: mac@1 {
  389. + compatible = "mediatek,eth-mac";
  390. + reg = <1>;
  391. + phy-mode = "2500base-x";
  392. + sfp = <&sfp1>;
  393. + managed = "in-band-status";
  394. + };
  395. +
  396. + mdio: mdio-bus {
  397. + #address-cells = <1>;
  398. + #size-cells = <0>;
  399. + };
  400. +};
  401. +
  402. +&mdio {
  403. + switch: switch@1f {
  404. + compatible = "mediatek,mt7531";
  405. + reg = <31>;
  406. + interrupt-controller;
  407. + #interrupt-cells = <1>;
  408. + interrupt-parent = <&pio>;
  409. + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
  410. + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
  411. + };
  412. +};
  413. +
  414. +&mmc0 {
  415. + pinctrl-names = "default", "state_uhs";
  416. + pinctrl-0 = <&mmc0_pins_default>;
  417. + pinctrl-1 = <&mmc0_pins_uhs>;
  418. + vmmc-supply = <&reg_3p3v>;
  419. + vqmmc-supply = <&reg_1p8v>;
  420. +};
  421. +
  422. +&i2c0 {
  423. + pinctrl-names = "default";
  424. + pinctrl-0 = <&i2c_pins>;
  425. + status = "okay";
  426. +};
  427. +
  428. +&pcie {
  429. + pinctrl-names = "default";
  430. + pinctrl-0 = <&pcie_pins>;
  431. + status = "okay";
  432. +};
  433. +
  434. +&pcie_phy {
  435. + status = "okay";
  436. +};
  437. +
  438. +&pio {
  439. + i2c_pins: i2c-pins {
  440. + mux {
  441. + function = "i2c";
  442. + groups = "i2c";
  443. + };
  444. + };
  445. +
  446. + mmc0_pins_default: mmc0-pins {
  447. + mux {
  448. + function = "emmc";
  449. + groups = "emmc_51";
  450. + };
  451. + conf-cmd-dat {
  452. + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
  453. + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
  454. + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
  455. + input-enable;
  456. + drive-strength = <4>;
  457. + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
  458. + };
  459. + conf-clk {
  460. + pins = "EMMC_CK";
  461. + drive-strength = <6>;
  462. + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
  463. + };
  464. + conf-ds {
  465. + pins = "EMMC_DSL";
  466. + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
  467. + };
  468. + conf-rst {
  469. + pins = "EMMC_RSTB";
  470. + drive-strength = <4>;
  471. + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
  472. + };
  473. + };
  474. +
  475. + mmc0_pins_uhs: mmc0-uhs-pins {
  476. + mux {
  477. + function = "emmc";
  478. + groups = "emmc_51";
  479. + };
  480. + conf-cmd-dat {
  481. + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
  482. + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
  483. + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
  484. + input-enable;
  485. + drive-strength = <4>;
  486. + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
  487. + };
  488. + conf-clk {
  489. + pins = "EMMC_CK";
  490. + drive-strength = <6>;
  491. + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
  492. + };
  493. + conf-ds {
  494. + pins = "EMMC_DSL";
  495. + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
  496. + };
  497. + conf-rst {
  498. + pins = "EMMC_RSTB";
  499. + drive-strength = <4>;
  500. + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
  501. + };
  502. + };
  503. +
  504. + pcie_pins: pcie-pins {
  505. + mux {
  506. + function = "pcie";
  507. + groups = "pcie_clk", "pcie_pereset";
  508. + };
  509. + };
  510. +
  511. + spi_flash_pins: spi-flash-pins {
  512. + mux {
  513. + function = "spi";
  514. + groups = "spi0", "spi0_wp_hold";
  515. + };
  516. + };
  517. +
  518. + spic_pins: spic-pins {
  519. + mux {
  520. + function = "spi";
  521. + groups = "spi1_0";
  522. + };
  523. + };
  524. +
  525. + uart1_pins: uart1-pins {
  526. + mux {
  527. + function = "uart";
  528. + groups = "uart1_rx_tx";
  529. + };
  530. + };
  531. +
  532. + uart2_pins: uart2-pins {
  533. + mux {
  534. + function = "uart";
  535. + groups = "uart2_0_rx_tx";
  536. + };
  537. + };
  538. +
  539. + wf_2g_5g_pins: wf-2g-5g-pins {
  540. + mux {
  541. + function = "wifi";
  542. + groups = "wf_2g", "wf_5g";
  543. + };
  544. + conf {
  545. + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
  546. + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
  547. + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
  548. + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
  549. + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
  550. + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
  551. + "WF1_TOP_CLK", "WF1_TOP_DATA";
  552. + drive-strength = <4>;
  553. + };
  554. + };
  555. +
  556. + wf_dbdc_pins: wf-dbdc-pins {
  557. + mux {
  558. + function = "wifi";
  559. + groups = "wf_dbdc";
  560. + };
  561. + conf {
  562. + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
  563. + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
  564. + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
  565. + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
  566. + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
  567. + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
  568. + "WF1_TOP_CLK", "WF1_TOP_DATA";
  569. + drive-strength = <4>;
  570. + };
  571. + };
  572. +
  573. + wf_led_pins: wf-led-pins {
  574. + mux {
  575. + function = "led";
  576. + groups = "wifi_led";
  577. + };
  578. + };
  579. +};
  580. +
  581. +&spi0 {
  582. + pinctrl-names = "default";
  583. + pinctrl-0 = <&spi_flash_pins>;
  584. + status = "okay";
  585. +};
  586. +
  587. +&spi1 {
  588. + pinctrl-names = "default";
  589. + pinctrl-0 = <&spic_pins>;
  590. + status = "okay";
  591. +};
  592. +
  593. +&ssusb {
  594. + status = "okay";
  595. +};
  596. +
  597. +&switch {
  598. + ports {
  599. + #address-cells = <1>;
  600. + #size-cells = <0>;
  601. +
  602. + port@0 {
  603. + reg = <0>;
  604. + label = "wan";
  605. + };
  606. +
  607. + port@1 {
  608. + reg = <1>;
  609. + label = "lan0";
  610. + };
  611. +
  612. + port@2 {
  613. + reg = <2>;
  614. + label = "lan1";
  615. + };
  616. +
  617. + port@3 {
  618. + reg = <3>;
  619. + label = "lan2";
  620. + };
  621. +
  622. + port@4 {
  623. + reg = <4>;
  624. + label = "lan3";
  625. + };
  626. +
  627. + port5: port@5 {
  628. + reg = <5>;
  629. + label = "lan4";
  630. + phy-mode = "2500base-x";
  631. + sfp = <&sfp2>;
  632. + managed = "in-band-status";
  633. + };
  634. +
  635. + port@6 {
  636. + reg = <6>;
  637. + label = "cpu";
  638. + ethernet = <&gmac0>;
  639. + phy-mode = "2500base-x";
  640. +
  641. + fixed-link {
  642. + speed = <2500>;
  643. + full-duplex;
  644. + pause;
  645. + };
  646. + };
  647. + };
  648. +};
  649. +
  650. +&trng {
  651. + status = "okay";
  652. +};
  653. +
  654. +&uart0 {
  655. + status = "okay";
  656. +};
  657. +
  658. +&uart1 {
  659. + pinctrl-names = "default";
  660. + pinctrl-0 = <&uart1_pins>;
  661. + status = "okay";
  662. +};
  663. +
  664. +&uart2 {
  665. + pinctrl-names = "default";
  666. + pinctrl-0 = <&uart2_pins>;
  667. + status = "okay";
  668. +};
  669. +
  670. +&usb_phy {
  671. + status = "okay";
  672. +};
  673. +
  674. +&watchdog {
  675. + status = "okay";
  676. +};
  677. +
  678. +&wifi {
  679. + status = "okay";
  680. + pinctrl-names = "default", "dbdc";
  681. + pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
  682. + pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
  683. +};
  684. +