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- From 06abdc84080729dc2c54946e1712c5ee1589ca1c Mon Sep 17 00:00:00 2001
- From: AngeloGioacchino Del Regno <[email protected]>
- Date: Mon, 6 Mar 2023 15:05:21 +0100
- Subject: [PATCH 13/15] clk: mediatek: mt7986-apmixed: Use PLL_AO flag to set
- critical clock
- Instead of calling clk_prepare_enable() at probe time, add the PLL_AO
- flag to CLK_APMIXED_ARMPLL clock: this will set CLK_IS_CRITICAL.
- Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
- Reviewed-by: Chen-Yu Tsai <[email protected]>
- Tested-by: Daniel Golle <[email protected]>
- Link: https://lore.kernel.org/r/20230306140543.1813621-33-angelogioacchino.delregno@collabora.com
- Signed-off-by: Stephen Boyd <[email protected]>
- ---
- drivers/clk/mediatek/clk-mt7986-apmixed.c | 4 +---
- 1 file changed, 1 insertion(+), 3 deletions(-)
- --- a/drivers/clk/mediatek/clk-mt7986-apmixed.c
- +++ b/drivers/clk/mediatek/clk-mt7986-apmixed.c
- @@ -42,7 +42,7 @@
- "clkxtal")
-
- static const struct mtk_pll_data plls[] = {
- - PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, 0, 32,
- + PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, PLL_AO, 32,
- 0x0200, 4, 0, 0x0204, 0),
- PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x0, 0, 32,
- 0x0210, 4, 0, 0x0214, 0),
- @@ -77,8 +77,6 @@ static int clk_mt7986_apmixed_probe(stru
-
- mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
-
- - clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
- -
- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
- if (r) {
- pr_err("%s(): could not register clock provider: %d\n",
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