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- From c202f510bbaa34ab5d65a69a61e0e72761374b17 Mon Sep 17 00:00:00 2001
- From: Daniel Golle <[email protected]>
- Date: Mon, 11 Mar 2024 17:14:19 +0000
- Subject: [PATCH] clk: mediatek: mt7988-infracfg: fix clocks for 2nd PCIe port
- Due to what seems to be an undocumented oddity in MediaTek's MT7988
- SoC design the CLK_INFRA_PCIE_PERI_26M_CK_P2 clock requires
- CLK_INFRA_PCIE_PERI_26M_CK_P3 to be enabled.
- This currently leads to PCIe port 2 not working in Linux.
- Reflect the apparent relationship in the clk driver to make sure PCIe
- port 2 of the MT7988 SoC works.
- Suggested-by: Sam Shih <[email protected]>
- Signed-off-by: Daniel Golle <[email protected]>
- ---
- drivers/clk/mediatek/clk-mt7988-infracfg.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
- --- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
- +++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
- @@ -156,7 +156,7 @@ static const struct mtk_gate infra_clks[
- GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, "infra_pcie_peri_ck_26m_ck_p1",
- "csw_infra_f26m_sel", 8),
- GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, "infra_pcie_peri_ck_26m_ck_p2",
- - "csw_infra_f26m_sel", 9),
- + "infra_pcie_peri_ck_26m_ck_p3", 9),
- GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, "infra_pcie_peri_ck_26m_ck_p3",
- "csw_infra_f26m_sel", 10),
- /* INFRA1 */
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