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704-include-linux-add-phy-hsgmii-mode.patch

704-include-linux-add-phy-hsgmii-mode.patch 2.1 KB
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  1. From 9d9bf16aa8d966834ac1280f96c37d22552c33d1 Mon Sep 17 00:00:00 2001
    2. 

  2. From: Birger Koblitz <[email protected]>
    3. 

  3. Date: Wed, 8 Sep 2021 16:13:18 +0200
    4. 

  4. Subject: phy: Add PHY hsgmii mode
    5. 

  5. 

  6. This adds RTL93xx-specific MAC configuration routines that allow also configuration
    7. 

  7. of 10GBit links for phylink. There is support for the Realtek-specific HISGMI
    8. 

  8. protocol.
    9. 

  9. 

  10. Submitted-by: Birger Koblitz <[email protected]>
    11. 

  11. ---
    12. 

  12.  drivers/net/phy/phylink.c                     | 2 ++
    13. 

  13.  include/linux/phy.h                           | 3 +++
    14. 

  14.  2 file changed, 5 insertions(+)
    15. 

  15. 

  16. --- a/drivers/net/phy/phy-core.c
    17. 

  17. +++ b/drivers/net/phy/phy-core.c
    18. 

  18. @@ -124,6 +124,7 @@ int phy_interface_num_ports(phy_interfac
    19. 

  19.  	case PHY_INTERFACE_MODE_MOCA:
    20. 

  20.  	case PHY_INTERFACE_MODE_TRGMII:
    21. 

  21.  	case PHY_INTERFACE_MODE_USXGMII:
    22. 

  22. +	case PHY_INTERFACE_MODE_HSGMII:
    23. 

  23.  	case PHY_INTERFACE_MODE_SGMII:
    24. 

  24.  	case PHY_INTERFACE_MODE_SMII:
    25. 

  25.  	case PHY_INTERFACE_MODE_1000BASEX:
    26. 

  26. --- a/drivers/net/phy/phylink.c
    27. 

  27. +++ b/drivers/net/phy/phylink.c
    28. 

  28. @@ -410,6 +410,7 @@ void phylink_get_linkmodes(unsigned long
    29. 

  29.  
    30. 

  30.  	case PHY_INTERFACE_MODE_XGMII:
    31. 

  31.  	case PHY_INTERFACE_MODE_RXAUI:
    32. 

  32. +	case PHY_INTERFACE_MODE_HSGMII:
    33. 

  33.  	case PHY_INTERFACE_MODE_XAUI:
    34. 

  34.  	case PHY_INTERFACE_MODE_10GBASER:
    35. 

  35.  	case PHY_INTERFACE_MODE_10GKR:
    36. 

  36. @@ -665,6 +666,7 @@ static int phylink_parse_mode(struct phy
    37. 

  37.  			fallthrough;
    38. 

  38.  		case PHY_INTERFACE_MODE_USXGMII:
    39. 

  39.  		case PHY_INTERFACE_MODE_10GKR:
    40. 

  40. +		case PHY_INTERFACE_MODE_HSGMII:
    41. 

  41.  		case PHY_INTERFACE_MODE_10GBASER:
    42. 

  42.  			phylink_set(pl->supported, 10baseT_Half);
    43. 

  43.  			phylink_set(pl->supported, 10baseT_Full);
    44. 

  44. --- a/include/linux/phy.h
    45. 

  45. +++ b/include/linux/phy.h
    46. 

  46. @@ -141,6 +141,7 @@ typedef enum {
    47. 

  47.  	PHY_INTERFACE_MODE_XGMII,
    48. 

  48.  	PHY_INTERFACE_MODE_XLGMII,
    49. 

  49.  	PHY_INTERFACE_MODE_MOCA,
    50. 

  50. +	PHY_INTERFACE_MODE_HSGMII,
    51. 

  51.  	PHY_INTERFACE_MODE_QSGMII,
    52. 

  52.  	PHY_INTERFACE_MODE_TRGMII,
    53. 

  53.  	PHY_INTERFACE_MODE_100BASEX,
    54. 

  54. @@ -248,6 +249,8 @@ static inline const char *phy_modes(phy_
    55. 

  55.  		return "xlgmii";
    56. 

  56.  	case PHY_INTERFACE_MODE_MOCA:
    57. 

  57.  		return "moca";
    58. 

  58. +	case PHY_INTERFACE_MODE_HSGMII:
    59. 

  59. +		return "hsgmii";
    60. 

  60.  	case PHY_INTERFACE_MODE_QSGMII:
    61. 

  61.  		return "qsgmii";
    62. 

  62.  	case PHY_INTERFACE_MODE_TRGMII:
    63.