0095-spi-cadence-quadspi-Add-support-for-StarFive-JH7110-.patch 2.5 KB

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  1. From a3749d68d81488ae07878393485278eab24a5818 Mon Sep 17 00:00:00 2001
  2. From: William Qiu <[email protected]>
  3. Date: Thu, 2 Mar 2023 18:52:21 +0800
  4. Subject: [PATCH 095/122] spi: cadence-quadspi: Add support for StarFive JH7110
  5. QSPI
  6. Add QSPI reset operation in device probe and add RISCV support to
  7. QUAD SPI Kconfig.
  8. Co-developed-by: Ziv Xu <[email protected]>
  9. Signed-off-by: Ziv Xu <[email protected]>
  10. Signed-off-by: William Qiu <[email protected]>
  11. ---
  12. drivers/spi/Kconfig | 2 +-
  13. drivers/spi/spi-cadence-quadspi.c | 21 ++++++++++++++++++++-
  14. 2 files changed, 21 insertions(+), 2 deletions(-)
  15. --- a/drivers/spi/Kconfig
  16. +++ b/drivers/spi/Kconfig
  17. @@ -230,7 +230,7 @@ config SPI_CADENCE
  18. config SPI_CADENCE_QUADSPI
  19. tristate "Cadence Quad SPI controller"
  20. - depends on OF && (ARM || ARM64 || X86 || COMPILE_TEST)
  21. + depends on OF && (ARM || ARM64 || X86 || RISCV || COMPILE_TEST)
  22. help
  23. Enable support for the Cadence Quad SPI Flash controller.
  24. --- a/drivers/spi/spi-cadence-quadspi.c
  25. +++ b/drivers/spi/spi-cadence-quadspi.c
  26. @@ -1575,7 +1575,7 @@ static int cqspi_setup_flash(struct cqsp
  27. static int cqspi_probe(struct platform_device *pdev)
  28. {
  29. const struct cqspi_driver_platdata *ddata;
  30. - struct reset_control *rstc, *rstc_ocp;
  31. + struct reset_control *rstc, *rstc_ocp, *rstc_ref;
  32. struct device *dev = &pdev->dev;
  33. struct spi_master *master;
  34. struct resource *res_ahb;
  35. @@ -1668,6 +1668,17 @@ static int cqspi_probe(struct platform_d
  36. goto probe_reset_failed;
  37. }
  38. + if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) {
  39. + rstc_ref = devm_reset_control_get_optional_exclusive(dev, "rstc_ref");
  40. + if (IS_ERR(rstc_ref)) {
  41. + ret = PTR_ERR(rstc_ref);
  42. + dev_err(dev, "Cannot get QSPI REF reset.\n");
  43. + goto probe_reset_failed;
  44. + }
  45. + reset_control_assert(rstc_ref);
  46. + reset_control_deassert(rstc_ref);
  47. + }
  48. +
  49. reset_control_assert(rstc);
  50. reset_control_deassert(rstc);
  51. @@ -1827,6 +1838,10 @@ static const struct cqspi_driver_platdat
  52. .get_dma_status = cqspi_get_versal_dma_status,
  53. };
  54. +static const struct cqspi_driver_platdata jh7110_qspi = {
  55. + .quirks = CQSPI_DISABLE_DAC_MODE,
  56. +};
  57. +
  58. static const struct of_device_id cqspi_dt_ids[] = {
  59. {
  60. .compatible = "cdns,qspi-nor",
  61. @@ -1852,6 +1867,10 @@ static const struct of_device_id cqspi_d
  62. .compatible = "intel,socfpga-qspi",
  63. .data = &socfpga_qspi,
  64. },
  65. + {
  66. + .compatible = "starfive,jh7110-qspi",
  67. + .data = &jh7110_qspi,
  68. + },
  69. { /* end of table */ }
  70. };