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1003-riscv-dts-starfive-Group-tuples-in-interrupt-propert.patch 1.5 KB

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  1. From 790e1157753b4dcc9bad4521987fe09aa6657876 Mon Sep 17 00:00:00 2001
  2. From: Geert Uytterhoeven <[email protected]>
  3. Date: Thu, 25 Nov 2021 14:21:18 +0100
  4. Subject: [PATCH 1003/1024] riscv: dts: starfive: Group tuples in interrupt
  5. properties
  6. To improve human readability and enable automatic validation, the tuples
  7. in the various properties containing interrupt specifiers should be
  8. grouped.
  9. Fix this by grouping the tuples of "interrupts-extended" properties
  10. using angle brackets.
  11. Signed-off-by: Geert Uytterhoeven <[email protected]>
  12. ---
  13. arch/riscv/boot/dts/starfive/jh7100.dtsi | 8 ++++----
  14. 1 file changed, 4 insertions(+), 4 deletions(-)
  15. --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
  16. +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
  17. @@ -118,15 +118,15 @@
  18. clint: clint@2000000 {
  19. compatible = "starfive,jh7100-clint", "sifive,clint0";
  20. reg = <0x0 0x2000000 0x0 0x10000>;
  21. - interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
  22. - &cpu1_intc 3 &cpu1_intc 7>;
  23. + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
  24. + <&cpu1_intc 3>, <&cpu1_intc 7>;
  25. };
  26. plic: interrupt-controller@c000000 {
  27. compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
  28. reg = <0x0 0xc000000 0x0 0x4000000>;
  29. - interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9
  30. - &cpu1_intc 11 &cpu1_intc 9>;
  31. + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
  32. + <&cpu1_intc 11>, <&cpu1_intc 9>;
  33. interrupt-controller;
  34. #address-cells = <0>;
  35. #interrupt-cells = <1>;