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1010-clk-starfive-Add-flags-argument-to-JH71X0__MUX-macro.patch

1010-clk-starfive-Add-flags-argument-to-JH71X0__MUX-macro.patch 14 KB
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  1. From f6c0c8639c7424f915f2f2f18cf86b6b97c7d32a Mon Sep 17 00:00:00 2001
    2. 

  2. From: Emil Renner Berthing <[email protected]>
    3. 

  3. Date: Sat, 25 Mar 2023 22:57:06 +0100
    4. 

  4. Subject: [PATCH 1010/1024] clk: starfive: Add flags argument to JH71X0__MUX
    5. 

  5.  macro
    6. 

  6. 

  7. This flag is needed to add the CLK_SET_RATE_PARENT flag on the gmac_tx
    8. 

  8. clock on the JH7100, which in turn is needed by the dwmac-starfive
    9. 

  9. driver to set the clock properly for 1000, 100 and 10 Mbps links.
    10. 

  10. 

  11. This change was mostly made using coccinelle:
    12. 

  12. 

  13. @ match @
    14. 

  14. expression idx, name, nparents;
    15. 

  15. @@
    16. 

  16.  JH71X0__MUX(
    17. 

  17. -idx, name, nparents,
    18. 

  18. +idx, name, 0, nparents,
    19. 

  19.  ...)
    20. 

  20. 

  21. Signed-off-by: Emil Renner Berthing <[email protected]>
    22. 

  22. ---
    23. 

  23.  .../clk/starfive/clk-starfive-jh7100-audio.c  |  2 +-
    24. 

  24.  drivers/clk/starfive/clk-starfive-jh7100.c    | 32 +++++++++----------
    25. 

  25.  .../clk/starfive/clk-starfive-jh7110-aon.c    |  6 ++--
    26. 

  26.  .../clk/starfive/clk-starfive-jh7110-isp.c    |  2 +-
    27. 

  27.  .../clk/starfive/clk-starfive-jh7110-sys.c    | 26 +++++++--------
    28. 

  28.  drivers/clk/starfive/clk-starfive-jh71x0.h    |  4 +--
    29. 

  29.  6 files changed, 36 insertions(+), 36 deletions(-)
    30. 

  30. 

  31. --- a/drivers/clk/starfive/clk-starfive-jh7100-audio.c
    32. 

  32. +++ b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
    33. 

  33. @@ -80,7 +80,7 @@ static const struct jh71x0_clk_data jh71
    34. 

  34.  	JH71X0_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB),
    35. 

  35.  	JH71X0_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB),
    36. 

  36.  	JH71X0__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),
    37. 

  37. -	JH71X0__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,
    38. 

  38. +	JH71X0__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 0, 2,
    39. 

  39.  		    JH7100_AUDCLK_VAD_INTMEM,
    40. 

  40.  		    JH7100_AUDCLK_AUDIO_12288),
    41. 

  41.  };
    42. 

  42. --- a/drivers/clk/starfive/clk-starfive-jh7100.c
    43. 

  43. +++ b/drivers/clk/starfive/clk-starfive-jh7100.c
    44. 

  44. @@ -24,48 +24,48 @@
    45. 

  45.  #define JH7100_CLK_GMAC_GR_MII_RX	(JH7100_CLK_END + 3)
    46. 

  46.  
    47. 

  47.  static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = {
    48. 

  48. -	JH71X0__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4,
    49. 

  49. +	JH71X0__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 0, 4,
    50. 

  50.  		    JH7100_CLK_OSC_SYS,
    51. 

  51.  		    JH7100_CLK_PLL0_OUT,
    52. 

  52.  		    JH7100_CLK_PLL1_OUT,
    53. 

  53.  		    JH7100_CLK_PLL2_OUT),
    54. 

  54. -	JH71X0__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3,
    55. 

  55. +	JH71X0__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 0, 3,
    56. 

  56.  		    JH7100_CLK_OSC_SYS,
    57. 

  57.  		    JH7100_CLK_PLL1_OUT,
    58. 

  58.  		    JH7100_CLK_PLL2_OUT),
    59. 

  59. -	JH71X0__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4,
    60. 

  60. +	JH71X0__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 0, 4,
    61. 

  61.  		    JH7100_CLK_OSC_SYS,
    62. 

  62.  		    JH7100_CLK_PLL0_OUT,
    63. 

  63.  		    JH7100_CLK_PLL1_OUT,
    64. 

  64.  		    JH7100_CLK_PLL2_OUT),
    65. 

  65. -	JH71X0__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3,
    66. 

  66. +	JH71X0__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 0, 3,
    67. 

  67.  		    JH7100_CLK_OSC_SYS,
    68. 

  68.  		    JH7100_CLK_PLL0_OUT,
    69. 

  69.  		    JH7100_CLK_PLL2_OUT),
    70. 

  70. -	JH71X0__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2,
    71. 

  71. +	JH71X0__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 0, 2,
    72. 

  72.  		    JH7100_CLK_OSC_SYS,
    73. 

  73.  		    JH7100_CLK_PLL0_OUT),
    74. 

  74. -	JH71X0__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2,
    75. 

  75. +	JH71X0__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 0, 2,
    76. 

  76.  		    JH7100_CLK_OSC_SYS,
    77. 

  77.  		    JH7100_CLK_PLL2_OUT),
    78. 

  78. -	JH71X0__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3,
    79. 

  79. +	JH71X0__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 0, 3,
    80. 

  80.  		    JH7100_CLK_OSC_SYS,
    81. 

  81.  		    JH7100_CLK_PLL1_OUT,
    82. 

  82.  		    JH7100_CLK_PLL2_OUT),
    83. 

  83. -	JH71X0__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3,
    84. 

  84. +	JH71X0__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 0, 3,
    85. 

  85.  		    JH7100_CLK_OSC_AUD,
    86. 

  86.  		    JH7100_CLK_PLL0_OUT,
    87. 

  87.  		    JH7100_CLK_PLL2_OUT),
    88. 

  88.  	JH71X0_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT),
    89. 

  89. -	JH71X0__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3,
    90. 

  90. +	JH71X0__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 0, 3,
    91. 

  91.  		    JH7100_CLK_OSC_SYS,
    92. 

  92.  		    JH7100_CLK_PLL1_OUT,
    93. 

  93.  		    JH7100_CLK_PLL2_OUT),
    94. 

  94. -	JH71X0__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3,
    95. 

  95. +	JH71X0__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 0, 3,
    96. 

  96.  		    JH7100_CLK_OSC_SYS,
    97. 

  97.  		    JH7100_CLK_PLL0_OUT,
    98. 

  98.  		    JH7100_CLK_PLL1_OUT),
    99. 

  99. -	JH71X0__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3,
    100. 

  100. +	JH71X0__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 0, 3,
    101. 

  101.  		    JH7100_CLK_OSC_AUD,
    102. 

  102.  		    JH7100_CLK_PLL0_OUT,
    103. 

  103.  		    JH7100_CLK_PLL2_OUT),
    104. 

  104. @@ -76,7 +76,7 @@ static const struct jh71x0_clk_data jh71
    105. 

  105.  	JH71X0_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC),
    106. 

  106.  	JH71X0_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT),
    107. 

  107.  	JH71X0_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC),
    108. 

  108. -	JH71X0__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2,
    109. 

  109. +	JH71X0__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 0, 2,
    110. 

  110.  		    JH7100_CLK_OSC_SYS,
    111. 

  111.  		    JH7100_CLK_OSC_AUD),
    112. 

  112.  	JH71X0__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
    113. 

  113. @@ -142,7 +142,7 @@ static const struct jh71x0_clk_data jh71
    114. 

  114.  	JH71X0__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT),
    115. 

  115.  	JH71X0_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS),
    116. 

  116.  	JH71X0__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT),
    117. 

  117. -	JH71X0__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2,
    118. 

  118. +	JH71X0__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 0, 2,
    119. 

  119.  		    JH7100_CLK_CPU_AXI,
    120. 

  120.  		    JH7100_CLK_NNEBUS_SRC1),
    121. 

  121.  	JH71X0_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS),
    122. 

  122. @@ -166,7 +166,7 @@ static const struct jh71x0_clk_data jh71
    123. 

  123.  	JH71X0_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV),
    124. 

  124.  	JH71X0_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32,
    125. 

  125.  		    JH7100_CLK_USBPHY_ROOTDIV),
    126. 

  126. -	JH71X0__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2,
    127. 

  127. +	JH71X0__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 0, 2,
    128. 

  128.  		    JH7100_CLK_OSC_SYS,
    129. 

  129.  		    JH7100_CLK_USBPHY_PLLDIV25M),
    130. 

  130.  	JH71X0_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT),
    131. 

  131. @@ -200,12 +200,12 @@ static const struct jh71x0_clk_data jh71
    132. 

  132.  	JH71X0_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV),
    133. 

  133.  	JH71X0_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
    134. 

  134.  	JH71X0_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
    135. 

  135. -	JH71X0__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3,
    136. 

  136. +	JH71X0__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 0, 3,
    137. 

  137.  		    JH7100_CLK_GMAC_GTX,
    138. 

  138.  		    JH7100_CLK_GMAC_TX_INV,
    139. 

  139.  		    JH7100_CLK_GMAC_RMII_TX),
    140. 

  140.  	JH71X0__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX),
    141. 

  141. -	JH71X0__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2,
    142. 

  142. +	JH71X0__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 0, 2,
    143. 

  143.  		    JH7100_CLK_GMAC_GR_MII_RX,
    144. 

  144.  		    JH7100_CLK_GMAC_RMII_RX),
    145. 

  145.  	JH71X0__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE),
    146. 

  146. --- a/drivers/clk/starfive/clk-starfive-jh7110-aon.c
    147. 

  147. +++ b/drivers/clk/starfive/clk-starfive-jh7110-aon.c
    148. 

  148. @@ -26,7 +26,7 @@
    149. 

  149.  static const struct jh71x0_clk_data jh7110_aonclk_data[] = {
    150. 

  150.  	/* source */
    151. 

  151.  	JH71X0__DIV(JH7110_AONCLK_OSC_DIV4, "osc_div4", 4, JH7110_AONCLK_OSC),
    152. 

  152. -	JH71X0__MUX(JH7110_AONCLK_APB_FUNC, "apb_func", 2,
    153. 

  153. +	JH71X0__MUX(JH7110_AONCLK_APB_FUNC, "apb_func", 0, 2,
    154. 

  154.  		    JH7110_AONCLK_OSC_DIV4,
    155. 

  155.  		    JH7110_AONCLK_OSC),
    156. 

  156.  	/* gmac0 */
    157. 

  157. @@ -39,7 +39,7 @@ static const struct jh71x0_clk_data jh71
    158. 

  158.  		    JH7110_AONCLK_GMAC0_GTXCLK,
    159. 

  159.  		    JH7110_AONCLK_GMAC0_RMII_RTX),
    160. 

  160.  	JH71X0__INV(JH7110_AONCLK_GMAC0_TX_INV, "gmac0_tx_inv", JH7110_AONCLK_GMAC0_TX),
    161. 

  161. -	JH71X0__MUX(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", 2,
    162. 

  162. +	JH71X0__MUX(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", 0, 2,
    163. 

  163.  		    JH7110_AONCLK_GMAC0_RGMII_RXIN,
    164. 

  164.  		    JH7110_AONCLK_GMAC0_RMII_RTX),
    165. 

  165.  	JH71X0__INV(JH7110_AONCLK_GMAC0_RX_INV, "gmac0_rx_inv", JH7110_AONCLK_GMAC0_RX),
    166. 

  166. @@ -48,7 +48,7 @@ static const struct jh71x0_clk_data jh71
    167. 

  167.  	/* rtc */
    168. 

  168.  	JH71X0_GATE(JH7110_AONCLK_RTC_APB, "rtc_apb", 0, JH7110_AONCLK_APB_BUS),
    169. 

  169.  	JH71X0__DIV(JH7110_AONCLK_RTC_INTERNAL, "rtc_internal", 1022, JH7110_AONCLK_OSC),
    170. 

  170. -	JH71X0__MUX(JH7110_AONCLK_RTC_32K, "rtc_32k", 2,
    171. 

  171. +	JH71X0__MUX(JH7110_AONCLK_RTC_32K, "rtc_32k", 0, 2,
    172. 

  172.  		    JH7110_AONCLK_RTC_OSC,
    173. 

  173.  		    JH7110_AONCLK_RTC_INTERNAL),
    174. 

  174.  	JH71X0_GATE(JH7110_AONCLK_RTC_CAL, "rtc_cal", 0, JH7110_AONCLK_OSC),
    175. 

  175. --- a/drivers/clk/starfive/clk-starfive-jh7110-isp.c
    176. 

  176. +++ b/drivers/clk/starfive/clk-starfive-jh7110-isp.c
    177. 

  177. @@ -53,7 +53,7 @@ static const struct jh71x0_clk_data jh71
    178. 

  178.  		    JH7110_ISPCLK_MIPI_RX0_PXL),
    179. 

  179.  	JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF3, "vin_pixel_if3", 0,
    180. 

  180.  		    JH7110_ISPCLK_MIPI_RX0_PXL),
    181. 

  181. -	JH71X0__MUX(JH7110_ISPCLK_VIN_P_AXI_WR, "vin_p_axi_wr", 2,
    182. 

  182. +	JH71X0__MUX(JH7110_ISPCLK_VIN_P_AXI_WR, "vin_p_axi_wr", 0, 2,
    183. 

  183.  		    JH7110_ISPCLK_MIPI_RX0_PXL,
    184. 

  184.  		    JH7110_ISPCLK_DVP_INV),
    185. 

  185.  	/* ispv2_top_wrapper */
    186. 

  186. --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
    187. 

  187. +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
    188. 

  188. @@ -36,18 +36,18 @@
    189. 

  189.  
    190. 

  190.  static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {
    191. 

  191.  	/* root */
    192. 

  192. -	JH71X0__MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", 2,
    193. 

  193. +	JH71X0__MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", 0, 2,
    194. 

  194.  		    JH7110_SYSCLK_OSC,
    195. 

  195.  		    JH7110_SYSCLK_PLL0_OUT),
    196. 

  196.  	JH71X0__DIV(JH7110_SYSCLK_CPU_CORE, "cpu_core", 7, JH7110_SYSCLK_CPU_ROOT),
    197. 

  197.  	JH71X0__DIV(JH7110_SYSCLK_CPU_BUS, "cpu_bus", 2, JH7110_SYSCLK_CPU_CORE),
    198. 

  198. -	JH71X0__MUX(JH7110_SYSCLK_GPU_ROOT, "gpu_root", 2,
    199. 

  199. +	JH71X0__MUX(JH7110_SYSCLK_GPU_ROOT, "gpu_root", 0, 2,
    200. 

  200.  		    JH7110_SYSCLK_PLL2_OUT,
    201. 

  201.  		    JH7110_SYSCLK_PLL1_OUT),
    202. 

  202.  	JH71X0_MDIV(JH7110_SYSCLK_PERH_ROOT, "perh_root", 2, 2,
    203. 

  203.  		    JH7110_SYSCLK_PLL0_OUT,
    204. 

  204.  		    JH7110_SYSCLK_PLL2_OUT),
    205. 

  205. -	JH71X0__MUX(JH7110_SYSCLK_BUS_ROOT, "bus_root", 2,
    206. 

  206. +	JH71X0__MUX(JH7110_SYSCLK_BUS_ROOT, "bus_root", 0, 2,
    207. 

  207.  		    JH7110_SYSCLK_OSC,
    208. 

  208.  		    JH7110_SYSCLK_PLL2_OUT),
    209. 

  209.  	JH71X0__DIV(JH7110_SYSCLK_NOCSTG_BUS, "nocstg_bus", 3, JH7110_SYSCLK_BUS_ROOT),
    210. 

  210. @@ -62,7 +62,7 @@ static const struct jh71x0_clk_data jh71
    211. 

  211.  	JH71X0__DIV(JH7110_SYSCLK_PLL2_DIV2, "pll2_div2", 2, JH7110_SYSCLK_PLL2_OUT),
    212. 

  212.  	JH71X0__DIV(JH7110_SYSCLK_AUDIO_ROOT, "audio_root", 8, JH7110_SYSCLK_PLL2_OUT),
    213. 

  213.  	JH71X0__DIV(JH7110_SYSCLK_MCLK_INNER, "mclk_inner", 64, JH7110_SYSCLK_AUDIO_ROOT),
    214. 

  214. -	JH71X0__MUX(JH7110_SYSCLK_MCLK, "mclk", 2,
    215. 

  215. +	JH71X0__MUX(JH7110_SYSCLK_MCLK, "mclk", 0, 2,
    216. 

  216.  		    JH7110_SYSCLK_MCLK_INNER,
    217. 

  217.  		    JH7110_SYSCLK_MCLK_EXT),
    218. 

  218.  	JH71X0_GATE(JH7110_SYSCLK_MCLK_OUT, "mclk_out", 0, JH7110_SYSCLK_MCLK_INNER),
    219. 

  219. @@ -96,7 +96,7 @@ static const struct jh71x0_clk_data jh71
    220. 

  220.  	JH71X0__DIV(JH7110_SYSCLK_OSC_DIV2, "osc_div2", 2, JH7110_SYSCLK_OSC),
    221. 

  221.  	JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV4, "pll1_div4", 2, JH7110_SYSCLK_PLL1_DIV2),
    222. 

  222.  	JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV8, "pll1_div8", 2, JH7110_SYSCLK_PLL1_DIV4),
    223. 

  223. -	JH71X0__MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", 4,
    224. 

  224. +	JH71X0__MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", 0, 4,
    225. 

  225.  		    JH7110_SYSCLK_OSC_DIV2,
    226. 

  226.  		    JH7110_SYSCLK_PLL1_DIV2,
    227. 

  227.  		    JH7110_SYSCLK_PLL1_DIV4,
    228. 

  228. @@ -186,7 +186,7 @@ static const struct jh71x0_clk_data jh71
    229. 

  229.  	JH71X0__DIV(JH7110_SYSCLK_GMAC1_RMII_RTX, "gmac1_rmii_rtx", 30,
    230. 

  230.  		    JH7110_SYSCLK_GMAC1_RMII_REFIN),
    231. 

  231.  	JH71X0_GDIV(JH7110_SYSCLK_GMAC1_PTP, "gmac1_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC),
    232. 

  232. -	JH71X0__MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", 2,
    233. 

  233. +	JH71X0__MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", 0, 2,
    234. 

  234.  		    JH7110_SYSCLK_GMAC1_RGMII_RXIN,
    235. 

  235.  		    JH7110_SYSCLK_GMAC1_RMII_RTX),
    236. 

  236.  	JH71X0__INV(JH7110_SYSCLK_GMAC1_RX_INV, "gmac1_rx_inv", JH7110_SYSCLK_GMAC1_RX),
    237. 

  237. @@ -270,11 +270,11 @@ static const struct jh71x0_clk_data jh71
    238. 

  238.  	JH71X0_MDIV(JH7110_SYSCLK_I2STX0_LRCK_MST, "i2stx0_lrck_mst", 64, 2,
    239. 

  239.  		    JH7110_SYSCLK_I2STX0_BCLK_MST_INV,
    240. 

  240.  		    JH7110_SYSCLK_I2STX0_BCLK_MST),
    241. 

  241. -	JH71X0__MUX(JH7110_SYSCLK_I2STX0_BCLK, "i2stx0_bclk",	2,
    242. 

  242. +	JH71X0__MUX(JH7110_SYSCLK_I2STX0_BCLK, "i2stx0_bclk", 0, 2,
    243. 

  243.  		    JH7110_SYSCLK_I2STX0_BCLK_MST,
    244. 

  244.  		    JH7110_SYSCLK_I2STX_BCLK_EXT),
    245. 

  245.  	JH71X0__INV(JH7110_SYSCLK_I2STX0_BCLK_INV, "i2stx0_bclk_inv", JH7110_SYSCLK_I2STX0_BCLK),
    246. 

  246. -	JH71X0__MUX(JH7110_SYSCLK_I2STX0_LRCK, "i2stx0_lrck", 2,
    247. 

  247. +	JH71X0__MUX(JH7110_SYSCLK_I2STX0_LRCK, "i2stx0_lrck", 0, 2,
    248. 

  248.  		    JH7110_SYSCLK_I2STX0_LRCK_MST,
    249. 

  249.  		    JH7110_SYSCLK_I2STX_LRCK_EXT),
    250. 

  250.  	/* i2stx1 */
    251. 

  251. @@ -285,11 +285,11 @@ static const struct jh71x0_clk_data jh71
    252. 

  252.  	JH71X0_MDIV(JH7110_SYSCLK_I2STX1_LRCK_MST, "i2stx1_lrck_mst", 64, 2,
    253. 

  253.  		    JH7110_SYSCLK_I2STX1_BCLK_MST_INV,
    254. 

  254.  		    JH7110_SYSCLK_I2STX1_BCLK_MST),
    255. 

  255. -	JH71X0__MUX(JH7110_SYSCLK_I2STX1_BCLK, "i2stx1_bclk", 2,
    256. 

  256. +	JH71X0__MUX(JH7110_SYSCLK_I2STX1_BCLK, "i2stx1_bclk", 0, 2,
    257. 

  257.  		    JH7110_SYSCLK_I2STX1_BCLK_MST,
    258. 

  258.  		    JH7110_SYSCLK_I2STX_BCLK_EXT),
    259. 

  259.  	JH71X0__INV(JH7110_SYSCLK_I2STX1_BCLK_INV, "i2stx1_bclk_inv", JH7110_SYSCLK_I2STX1_BCLK),
    260. 

  260. -	JH71X0__MUX(JH7110_SYSCLK_I2STX1_LRCK, "i2stx1_lrck", 2,
    261. 

  261. +	JH71X0__MUX(JH7110_SYSCLK_I2STX1_LRCK, "i2stx1_lrck", 0, 2,
    262. 

  262.  		    JH7110_SYSCLK_I2STX1_LRCK_MST,
    263. 

  263.  		    JH7110_SYSCLK_I2STX_LRCK_EXT),
    264. 

  264.  	/* i2srx */
    265. 

  265. @@ -300,11 +300,11 @@ static const struct jh71x0_clk_data jh71
    266. 

  266.  	JH71X0_MDIV(JH7110_SYSCLK_I2SRX_LRCK_MST, "i2srx_lrck_mst", 64, 2,
    267. 

  267.  		    JH7110_SYSCLK_I2SRX_BCLK_MST_INV,
    268. 

  268.  		    JH7110_SYSCLK_I2SRX_BCLK_MST),
    269. 

  269. -	JH71X0__MUX(JH7110_SYSCLK_I2SRX_BCLK, "i2srx_bclk", 2,
    270. 

  270. +	JH71X0__MUX(JH7110_SYSCLK_I2SRX_BCLK, "i2srx_bclk", 0, 2,
    271. 

  271.  		    JH7110_SYSCLK_I2SRX_BCLK_MST,
    272. 

  272.  		    JH7110_SYSCLK_I2SRX_BCLK_EXT),
    273. 

  273.  	JH71X0__INV(JH7110_SYSCLK_I2SRX_BCLK_INV, "i2srx_bclk_inv", JH7110_SYSCLK_I2SRX_BCLK),
    274. 

  274. -	JH71X0__MUX(JH7110_SYSCLK_I2SRX_LRCK, "i2srx_lrck", 2,
    275. 

  275. +	JH71X0__MUX(JH7110_SYSCLK_I2SRX_LRCK, "i2srx_lrck", 0, 2,
    276. 

  276.  		    JH7110_SYSCLK_I2SRX_LRCK_MST,
    277. 

  277.  		    JH7110_SYSCLK_I2SRX_LRCK_EXT),
    278. 

  278.  	/* pdm */
    279. 

  279. @@ -314,7 +314,7 @@ static const struct jh71x0_clk_data jh71
    280. 

  280.  	JH71X0_GATE(JH7110_SYSCLK_TDM_AHB, "tdm_ahb", 0, JH7110_SYSCLK_AHB0),
    281. 

  281.  	JH71X0_GATE(JH7110_SYSCLK_TDM_APB, "tdm_apb", 0, JH7110_SYSCLK_APB0),
    282. 

  282.  	JH71X0_GDIV(JH7110_SYSCLK_TDM_INTERNAL, "tdm_internal", 0, 64, JH7110_SYSCLK_MCLK),
    283. 

  283. -	JH71X0__MUX(JH7110_SYSCLK_TDM_TDM, "tdm_tdm", 2,
    284. 

  284. +	JH71X0__MUX(JH7110_SYSCLK_TDM_TDM, "tdm_tdm", 0, 2,
    285. 

  285.  		    JH7110_SYSCLK_TDM_INTERNAL,
    286. 

  286.  		    JH7110_SYSCLK_TDM_EXT),
    287. 

  287.  	JH71X0__INV(JH7110_SYSCLK_TDM_TDM_INV, "tdm_tdm_inv", JH7110_SYSCLK_TDM_TDM),
    288. 

  288. --- a/drivers/clk/starfive/clk-starfive-jh71x0.h
    289. 

  289. +++ b/drivers/clk/starfive/clk-starfive-jh71x0.h
    290. 

  290. @@ -61,10 +61,10 @@ struct jh71x0_clk_data {
    291. 

  291.  	.parents = { [0] = _parent },						\
    292. 

  292.  }
    293. 

  293.  
    294. 

  294. -#define JH71X0__MUX(_idx, _name, _nparents, ...)				\
    295. 

  295. +#define JH71X0__MUX(_idx, _name, _flags, _nparents, ...)			\
    296. 

  296.  [_idx] = {									\
    297. 

  297.  	.name = _name,								\
    298. 

  298. -	.flags = 0,								\
    299. 

  299. +	.flags = _flags,							\
    300. 

  300.  	.max = ((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT,			\
    301. 

  301.  	.parents = { __VA_ARGS__ },						\
    302. 

  302.  }
    303.