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- From cd833f484009f37be57a2aa09257af6e8c1b25b6 Mon Sep 17 00:00:00 2001
- From: Emil Renner Berthing <[email protected]>
- Date: Sat, 1 Apr 2023 19:19:14 +0800
- Subject: [PATCH 002/122] dt-bindings: clock: Add StarFive JH7110 always-on
- clock and reset generator
- Add bindings for the always-on clock and reset generator (AONCRG) on the
- JH7110 RISC-V SoC by StarFive Ltd.
- Reviewed-by: Conor Dooley <[email protected]>
- Reviewed-by: Rob Herring <[email protected]>
- Reviewed-by: Emil Renner Berthing <[email protected]>
- Signed-off-by: Emil Renner Berthing <[email protected]>
- Signed-off-by: Hal Feng <[email protected]>
- Signed-off-by: Conor Dooley <[email protected]>
- ---
- .../clock/starfive,jh7110-aoncrg.yaml | 107 ++++++++++++++++++
- .../dt-bindings/clock/starfive,jh7110-crg.h | 18 +++
- .../dt-bindings/reset/starfive,jh7110-crg.h | 12 ++
- 3 files changed, 137 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
- --- /dev/null
- +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
- @@ -0,0 +1,107 @@
- +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
- +%YAML 1.2
- +---
- +$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#
- +$schema: http://devicetree.org/meta-schemas/core.yaml#
- +
- +title: StarFive JH7110 Always-On Clock and Reset Generator
- +
- +maintainers:
- + - Emil Renner Berthing <[email protected]>
- +
- +properties:
- + compatible:
- + const: starfive,jh7110-aoncrg
- +
- + reg:
- + maxItems: 1
- +
- + clocks:
- + oneOf:
- + - items:
- + - description: Main Oscillator (24 MHz)
- + - description: GMAC0 RMII reference or GMAC0 RGMII RX
- + - description: STG AXI/AHB
- + - description: APB Bus
- + - description: GMAC0 GTX
- +
- + - items:
- + - description: Main Oscillator (24 MHz)
- + - description: GMAC0 RMII reference or GMAC0 RGMII RX
- + - description: STG AXI/AHB or GMAC0 RGMII RX
- + - description: APB Bus or STG AXI/AHB
- + - description: GMAC0 GTX or APB Bus
- + - description: RTC Oscillator (32.768 kHz) or GMAC0 GTX
- +
- + - items:
- + - description: Main Oscillator (24 MHz)
- + - description: GMAC0 RMII reference
- + - description: GMAC0 RGMII RX
- + - description: STG AXI/AHB
- + - description: APB Bus
- + - description: GMAC0 GTX
- + - description: RTC Oscillator (32.768 kHz)
- +
- + clock-names:
- + oneOf:
- + - minItems: 5
- + items:
- + - const: osc
- + - enum:
- + - gmac0_rmii_refin
- + - gmac0_rgmii_rxin
- + - const: stg_axiahb
- + - const: apb_bus
- + - const: gmac0_gtxclk
- + - const: rtc_osc
- +
- + - minItems: 6
- + items:
- + - const: osc
- + - const: gmac0_rmii_refin
- + - const: gmac0_rgmii_rxin
- + - const: stg_axiahb
- + - const: apb_bus
- + - const: gmac0_gtxclk
- + - const: rtc_osc
- +
- + '#clock-cells':
- + const: 1
- + description:
- + See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
- +
- + '#reset-cells':
- + const: 1
- + description:
- + See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
- +
- +required:
- + - compatible
- + - reg
- + - clocks
- + - clock-names
- + - '#clock-cells'
- + - '#reset-cells'
- +
- +additionalProperties: false
- +
- +examples:
- + - |
- + #include <dt-bindings/clock/starfive,jh7110-crg.h>
- +
- + clock-controller@17000000 {
- + compatible = "starfive,jh7110-aoncrg";
- + reg = <0x17000000 0x10000>;
- + clocks = <&osc>, <&gmac0_rmii_refin>,
- + <&gmac0_rgmii_rxin>,
- + <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
- + <&syscrg JH7110_SYSCLK_APB_BUS>,
- + <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,
- + <&rtc_osc>;
- + clock-names = "osc", "gmac0_rmii_refin",
- + "gmac0_rgmii_rxin", "stg_axiahb",
- + "apb_bus", "gmac0_gtxclk",
- + "rtc_osc";
- + #clock-cells = <1>;
- + #reset-cells = <1>;
- + };
- --- a/include/dt-bindings/clock/starfive,jh7110-crg.h
- +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
- @@ -200,4 +200,22 @@
-
- #define JH7110_SYSCLK_END 190
-
- +/* AONCRG clocks */
- +#define JH7110_AONCLK_OSC_DIV4 0
- +#define JH7110_AONCLK_APB_FUNC 1
- +#define JH7110_AONCLK_GMAC0_AHB 2
- +#define JH7110_AONCLK_GMAC0_AXI 3
- +#define JH7110_AONCLK_GMAC0_RMII_RTX 4
- +#define JH7110_AONCLK_GMAC0_TX 5
- +#define JH7110_AONCLK_GMAC0_TX_INV 6
- +#define JH7110_AONCLK_GMAC0_RX 7
- +#define JH7110_AONCLK_GMAC0_RX_INV 8
- +#define JH7110_AONCLK_OTPC_APB 9
- +#define JH7110_AONCLK_RTC_APB 10
- +#define JH7110_AONCLK_RTC_INTERNAL 11
- +#define JH7110_AONCLK_RTC_32K 12
- +#define JH7110_AONCLK_RTC_CAL 13
- +
- +#define JH7110_AONCLK_END 14
- +
- #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */
- --- a/include/dt-bindings/reset/starfive,jh7110-crg.h
- +++ b/include/dt-bindings/reset/starfive,jh7110-crg.h
- @@ -139,4 +139,16 @@
-
- #define JH7110_SYSRST_END 126
-
- +/* AONCRG resets */
- +#define JH7110_AONRST_GMAC0_AXI 0
- +#define JH7110_AONRST_GMAC0_AHB 1
- +#define JH7110_AONRST_IOMUX 2
- +#define JH7110_AONRST_PMU_APB 3
- +#define JH7110_AONRST_PMU_WKUP 4
- +#define JH7110_AONRST_RTC_APB 5
- +#define JH7110_AONRST_RTC_CAL 6
- +#define JH7110_AONRST_RTC_32K 7
- +
- +#define JH7110_AONRST_END 8
- +
- #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */
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