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0013-clk-starfive-Add-StarFive-JH7110-system-clock-driver.patch

0013-clk-starfive-Add-StarFive-JH7110-system-clock-driver.patch 25 KB
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  1. From eea853275c704f6c24a418a50715bc5ad68a6283 Mon Sep 17 00:00:00 2001
    2. 

  2. From: Emil Renner Berthing <[email protected]>
    3. 

  3. Date: Sat, 1 Apr 2023 19:19:25 +0800
    4. 

  4. Subject: [PATCH 013/122] clk: starfive: Add StarFive JH7110 system clock
    5. 

  5.  driver
    6. 

  6. 

  7. Add driver for the StarFive JH7110 system clock controller and
    8. 

  8. register an auxiliary device for system reset controller which
    9. 

  9. is named as "rst-sys".
    10. 

  10. 

  11. Tested-by: Tommaso Merciai <[email protected]>
    12. 

  12. Reviewed-by: Emil Renner Berthing <[email protected]>
    13. 

  13. Signed-off-by: Emil Renner Berthing <[email protected]>
    14. 

  14. Co-developed-by: Hal Feng <[email protected]>
    15. 

  15. Signed-off-by: Hal Feng <[email protected]>
    16. 

  16. Signed-off-by: Conor Dooley <[email protected]>
    17. 

  17. ---
    18. 

  18.  drivers/clk/starfive/Kconfig                  |  11 +
    19. 

  19.  drivers/clk/starfive/Makefile                 |   2 +
    20. 

  20.  .../clk/starfive/clk-starfive-jh7110-sys.c    | 490 ++++++++++++++++++
    21. 

  21.  drivers/clk/starfive/clk-starfive-jh7110.h    |  11 +
    22. 

  22.  4 files changed, 514 insertions(+)
    23. 

  23.  create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-sys.c
    24. 

  24.  create mode 100644 drivers/clk/starfive/clk-starfive-jh7110.h
    25. 

  25. 

  26. --- a/drivers/clk/starfive/Kconfig
    27. 

  27. +++ b/drivers/clk/starfive/Kconfig
    28. 

  28. @@ -20,3 +20,14 @@ config CLK_STARFIVE_JH7100_AUDIO
    29. 

  29.  	help
    30. 

  30.  	  Say Y or M here to support the audio clocks on the StarFive JH7100
    31. 

  31.  	  SoC.
    32. 

  32. +
    33. 

  33. +config CLK_STARFIVE_JH7110_SYS
    34. 

  34. +	bool "StarFive JH7110 system clock support"
    35. 

  35. +	depends on ARCH_STARFIVE || COMPILE_TEST
    36. 

  36. +	select AUXILIARY_BUS
    37. 

  37. +	select CLK_STARFIVE_JH71X0
    38. 

  38. +	select RESET_STARFIVE_JH7110
    39. 

  39. +	default ARCH_STARFIVE
    40. 

  40. +	help
    41. 

  41. +	  Say yes here to support the system clock controller on the
    42. 

  42. +	  StarFive JH7110 SoC.
    43. 

  43. --- a/drivers/clk/starfive/Makefile
    44. 

  44. +++ b/drivers/clk/starfive/Makefile
    45. 

  45. @@ -3,3 +3,5 @@ obj-$(CONFIG_CLK_STARFIVE_JH71X0)	+= clk
    46. 

  46.  
    47. 

  47.  obj-$(CONFIG_CLK_STARFIVE_JH7100)	+= clk-starfive-jh7100.o
    48. 

  48.  obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO)	+= clk-starfive-jh7100-audio.o
    49. 

  49. +
    50. 

  50. +obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS)	+= clk-starfive-jh7110-sys.o
    51. 

  51. --- /dev/null
    52. 

  52. +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
    53. 

  53. @@ -0,0 +1,490 @@
    54. 

  54. +// SPDX-License-Identifier: GPL-2.0
    55. 

  55. +/*
    56. 

  56. + * StarFive JH7110 System Clock Driver
    57. 

  57. + *
    58. 

  58. + * Copyright (C) 2022 Emil Renner Berthing <[email protected]>
    59. 

  59. + * Copyright (C) 2022 StarFive Technology Co., Ltd.
    60. 

  60. + */
    61. 

  61. +
    62. 

  62. +#include <linux/auxiliary_bus.h>
    63. 

  63. +#include <linux/clk-provider.h>
    64. 

  64. +#include <linux/init.h>
    65. 

  65. +#include <linux/io.h>
    66. 

  66. +#include <linux/platform_device.h>
    67. 

  67. +
    68. 

  68. +#include <dt-bindings/clock/starfive,jh7110-crg.h>
    69. 

  69. +
    70. 

  70. +#include "clk-starfive-jh7110.h"
    71. 

  71. +
    72. 

  72. +/* external clocks */
    73. 

  73. +#define JH7110_SYSCLK_OSC			(JH7110_SYSCLK_END + 0)
    74. 

  74. +#define JH7110_SYSCLK_GMAC1_RMII_REFIN		(JH7110_SYSCLK_END + 1)
    75. 

  75. +#define JH7110_SYSCLK_GMAC1_RGMII_RXIN		(JH7110_SYSCLK_END + 2)
    76. 

  76. +#define JH7110_SYSCLK_I2STX_BCLK_EXT		(JH7110_SYSCLK_END + 3)
    77. 

  77. +#define JH7110_SYSCLK_I2STX_LRCK_EXT		(JH7110_SYSCLK_END + 4)
    78. 

  78. +#define JH7110_SYSCLK_I2SRX_BCLK_EXT		(JH7110_SYSCLK_END + 5)
    79. 

  79. +#define JH7110_SYSCLK_I2SRX_LRCK_EXT		(JH7110_SYSCLK_END + 6)
    80. 

  80. +#define JH7110_SYSCLK_TDM_EXT			(JH7110_SYSCLK_END + 7)
    81. 

  81. +#define JH7110_SYSCLK_MCLK_EXT			(JH7110_SYSCLK_END + 8)
    82. 

  82. +#define JH7110_SYSCLK_PLL0_OUT			(JH7110_SYSCLK_END + 9)
    83. 

  83. +#define JH7110_SYSCLK_PLL1_OUT			(JH7110_SYSCLK_END + 10)
    84. 

  84. +#define JH7110_SYSCLK_PLL2_OUT			(JH7110_SYSCLK_END + 11)
    85. 

  85. +
    86. 

  86. +static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {
    87. 

  87. +	/* root */
    88. 

  88. +	JH71X0__MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", 2,
    89. 

  89. +		    JH7110_SYSCLK_OSC,
    90. 

  90. +		    JH7110_SYSCLK_PLL0_OUT),
    91. 

  91. +	JH71X0__DIV(JH7110_SYSCLK_CPU_CORE, "cpu_core", 7, JH7110_SYSCLK_CPU_ROOT),
    92. 

  92. +	JH71X0__DIV(JH7110_SYSCLK_CPU_BUS, "cpu_bus", 2, JH7110_SYSCLK_CPU_CORE),
    93. 

  93. +	JH71X0__MUX(JH7110_SYSCLK_GPU_ROOT, "gpu_root", 2,
    94. 

  94. +		    JH7110_SYSCLK_PLL2_OUT,
    95. 

  95. +		    JH7110_SYSCLK_PLL1_OUT),
    96. 

  96. +	JH71X0_MDIV(JH7110_SYSCLK_PERH_ROOT, "perh_root", 2, 2,
    97. 

  97. +		    JH7110_SYSCLK_PLL0_OUT,
    98. 

  98. +		    JH7110_SYSCLK_PLL2_OUT),
    99. 

  99. +	JH71X0__MUX(JH7110_SYSCLK_BUS_ROOT, "bus_root", 2,
    100. 

  100. +		    JH7110_SYSCLK_OSC,
    101. 

  101. +		    JH7110_SYSCLK_PLL2_OUT),
    102. 

  102. +	JH71X0__DIV(JH7110_SYSCLK_NOCSTG_BUS, "nocstg_bus", 3, JH7110_SYSCLK_BUS_ROOT),
    103. 

  103. +	JH71X0__DIV(JH7110_SYSCLK_AXI_CFG0, "axi_cfg0", 3, JH7110_SYSCLK_BUS_ROOT),
    104. 

  104. +	JH71X0__DIV(JH7110_SYSCLK_STG_AXIAHB, "stg_axiahb", 2, JH7110_SYSCLK_AXI_CFG0),
    105. 

  105. +	JH71X0_GATE(JH7110_SYSCLK_AHB0, "ahb0", CLK_IS_CRITICAL, JH7110_SYSCLK_STG_AXIAHB),
    106. 

  106. +	JH71X0_GATE(JH7110_SYSCLK_AHB1, "ahb1", CLK_IS_CRITICAL, JH7110_SYSCLK_STG_AXIAHB),
    107. 

  107. +	JH71X0__DIV(JH7110_SYSCLK_APB_BUS, "apb_bus", 8, JH7110_SYSCLK_STG_AXIAHB),
    108. 

  108. +	JH71X0_GATE(JH7110_SYSCLK_APB0, "apb0", CLK_IS_CRITICAL, JH7110_SYSCLK_APB_BUS),
    109. 

  109. +	JH71X0__DIV(JH7110_SYSCLK_PLL0_DIV2, "pll0_div2", 2, JH7110_SYSCLK_PLL0_OUT),
    110. 

  110. +	JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV2, "pll1_div2", 2, JH7110_SYSCLK_PLL1_OUT),
    111. 

  111. +	JH71X0__DIV(JH7110_SYSCLK_PLL2_DIV2, "pll2_div2", 2, JH7110_SYSCLK_PLL2_OUT),
    112. 

  112. +	JH71X0__DIV(JH7110_SYSCLK_AUDIO_ROOT, "audio_root", 8, JH7110_SYSCLK_PLL2_OUT),
    113. 

  113. +	JH71X0__DIV(JH7110_SYSCLK_MCLK_INNER, "mclk_inner", 64, JH7110_SYSCLK_AUDIO_ROOT),
    114. 

  114. +	JH71X0__MUX(JH7110_SYSCLK_MCLK, "mclk", 2,
    115. 

  115. +		    JH7110_SYSCLK_MCLK_INNER,
    116. 

  116. +		    JH7110_SYSCLK_MCLK_EXT),
    117. 

  117. +	JH71X0_GATE(JH7110_SYSCLK_MCLK_OUT, "mclk_out", 0, JH7110_SYSCLK_MCLK_INNER),
    118. 

  118. +	JH71X0_MDIV(JH7110_SYSCLK_ISP_2X, "isp_2x", 8, 2,
    119. 

  119. +		    JH7110_SYSCLK_PLL2_OUT,
    120. 

  120. +		    JH7110_SYSCLK_PLL1_OUT),
    121. 

  121. +	JH71X0__DIV(JH7110_SYSCLK_ISP_AXI, "isp_axi", 4, JH7110_SYSCLK_ISP_2X),
    122. 

  122. +	JH71X0_GDIV(JH7110_SYSCLK_GCLK0, "gclk0", 0, 62, JH7110_SYSCLK_PLL0_DIV2),
    123. 

  123. +	JH71X0_GDIV(JH7110_SYSCLK_GCLK1, "gclk1", 0, 62, JH7110_SYSCLK_PLL1_DIV2),
    124. 

  124. +	JH71X0_GDIV(JH7110_SYSCLK_GCLK2, "gclk2", 0, 62, JH7110_SYSCLK_PLL2_DIV2),
    125. 

  125. +	/* cores */
    126. 

  126. +	JH71X0_GATE(JH7110_SYSCLK_CORE, "core", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
    127. 

  127. +	JH71X0_GATE(JH7110_SYSCLK_CORE1, "core1", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
    128. 

  128. +	JH71X0_GATE(JH7110_SYSCLK_CORE2, "core2", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
    129. 

  129. +	JH71X0_GATE(JH7110_SYSCLK_CORE3, "core3", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
    130. 

  130. +	JH71X0_GATE(JH7110_SYSCLK_CORE4, "core4", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
    131. 

  131. +	JH71X0_GATE(JH7110_SYSCLK_DEBUG, "debug", 0, JH7110_SYSCLK_CPU_BUS),
    132. 

  132. +	JH71X0__DIV(JH7110_SYSCLK_RTC_TOGGLE, "rtc_toggle", 6, JH7110_SYSCLK_OSC),
    133. 

  133. +	JH71X0_GATE(JH7110_SYSCLK_TRACE0, "trace0", 0, JH7110_SYSCLK_CPU_CORE),
    134. 

  134. +	JH71X0_GATE(JH7110_SYSCLK_TRACE1, "trace1", 0, JH7110_SYSCLK_CPU_CORE),
    135. 

  135. +	JH71X0_GATE(JH7110_SYSCLK_TRACE2, "trace2", 0, JH7110_SYSCLK_CPU_CORE),
    136. 

  136. +	JH71X0_GATE(JH7110_SYSCLK_TRACE3, "trace3", 0, JH7110_SYSCLK_CPU_CORE),
    137. 

  137. +	JH71X0_GATE(JH7110_SYSCLK_TRACE4, "trace4", 0, JH7110_SYSCLK_CPU_CORE),
    138. 

  138. +	JH71X0_GATE(JH7110_SYSCLK_TRACE_COM, "trace_com", 0, JH7110_SYSCLK_CPU_BUS),
    139. 

  139. +	/* noc */
    140. 

  140. +	JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_CPU_AXI, "noc_bus_cpu_axi", CLK_IS_CRITICAL,
    141. 

  141. +		    JH7110_SYSCLK_CPU_BUS),
    142. 

  142. +	JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI, "noc_bus_axicfg0_axi", CLK_IS_CRITICAL,
    143. 

  143. +		    JH7110_SYSCLK_AXI_CFG0),
    144. 

  144. +	/* ddr */
    145. 

  145. +	JH71X0__DIV(JH7110_SYSCLK_OSC_DIV2, "osc_div2", 2, JH7110_SYSCLK_OSC),
    146. 

  146. +	JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV4, "pll1_div4", 2, JH7110_SYSCLK_PLL1_DIV2),
    147. 

  147. +	JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV8, "pll1_div8", 2, JH7110_SYSCLK_PLL1_DIV4),
    148. 

  148. +	JH71X0__MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", 4,
    149. 

  149. +		    JH7110_SYSCLK_OSC_DIV2,
    150. 

  150. +		    JH7110_SYSCLK_PLL1_DIV2,
    151. 

  151. +		    JH7110_SYSCLK_PLL1_DIV4,
    152. 

  152. +		    JH7110_SYSCLK_PLL1_DIV8),
    153. 

  153. +	JH71X0_GATE(JH7110_SYSCLK_DDR_AXI, "ddr_axi", CLK_IS_CRITICAL, JH7110_SYSCLK_DDR_BUS),
    154. 

  154. +	/* gpu */
    155. 

  155. +	JH71X0__DIV(JH7110_SYSCLK_GPU_CORE, "gpu_core", 7, JH7110_SYSCLK_GPU_ROOT),
    156. 

  156. +	JH71X0_GATE(JH7110_SYSCLK_GPU_CORE_CLK, "gpu_core_clk", 0, JH7110_SYSCLK_GPU_CORE),
    157. 

  157. +	JH71X0_GATE(JH7110_SYSCLK_GPU_SYS_CLK, "gpu_sys_clk", 0, JH7110_SYSCLK_ISP_AXI),
    158. 

  158. +	JH71X0_GATE(JH7110_SYSCLK_GPU_APB, "gpu_apb", 0, JH7110_SYSCLK_APB_BUS),
    159. 

  159. +	JH71X0_GDIV(JH7110_SYSCLK_GPU_RTC_TOGGLE, "gpu_rtc_toggle", 0, 12, JH7110_SYSCLK_OSC),
    160. 

  160. +	JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_GPU_AXI, "noc_bus_gpu_axi", 0, JH7110_SYSCLK_GPU_CORE),
    161. 

  161. +	/* isp */
    162. 

  162. +	JH71X0_GATE(JH7110_SYSCLK_ISP_TOP_CORE, "isp_top_core", 0, JH7110_SYSCLK_ISP_2X),
    163. 

  163. +	JH71X0_GATE(JH7110_SYSCLK_ISP_TOP_AXI, "isp_top_axi", 0, JH7110_SYSCLK_ISP_AXI),
    164. 

  164. +	JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_ISP_AXI, "noc_bus_isp_axi", CLK_IS_CRITICAL,
    165. 

  165. +		    JH7110_SYSCLK_ISP_AXI),
    166. 

  166. +	/* hifi4 */
    167. 

  167. +	JH71X0__DIV(JH7110_SYSCLK_HIFI4_CORE, "hifi4_core", 15, JH7110_SYSCLK_BUS_ROOT),
    168. 

  168. +	JH71X0__DIV(JH7110_SYSCLK_HIFI4_AXI, "hifi4_axi", 2, JH7110_SYSCLK_HIFI4_CORE),
    169. 

  169. +	/* axi_cfg1 */
    170. 

  170. +	JH71X0_GATE(JH7110_SYSCLK_AXI_CFG1_MAIN, "axi_cfg1_main", CLK_IS_CRITICAL,
    171. 

  171. +		    JH7110_SYSCLK_ISP_AXI),
    172. 

  172. +	JH71X0_GATE(JH7110_SYSCLK_AXI_CFG1_AHB, "axi_cfg1_ahb", CLK_IS_CRITICAL,
    173. 

  173. +		    JH7110_SYSCLK_AHB0),
    174. 

  174. +	/* vout */
    175. 

  175. +	JH71X0_GATE(JH7110_SYSCLK_VOUT_SRC, "vout_src", 0, JH7110_SYSCLK_PLL2_OUT),
    176. 

  176. +	JH71X0__DIV(JH7110_SYSCLK_VOUT_AXI, "vout_axi", 7, JH7110_SYSCLK_PLL2_OUT),
    177. 

  177. +	JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_DISP_AXI, "noc_bus_disp_axi", 0, JH7110_SYSCLK_VOUT_AXI),
    178. 

  178. +	JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_AHB, "vout_top_ahb", 0, JH7110_SYSCLK_AHB1),
    179. 

  179. +	JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_AXI, "vout_top_axi", 0, JH7110_SYSCLK_VOUT_AXI),
    180. 

  180. +	JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK, "vout_top_hdmitx0_mclk", 0,
    181. 

  181. +		    JH7110_SYSCLK_MCLK),
    182. 

  182. +	JH71X0__DIV(JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF, "vout_top_mipiphy_ref", 2,
    183. 

  183. +		    JH7110_SYSCLK_OSC),
    184. 

  184. +	/* jpegc */
    185. 

  185. +	JH71X0__DIV(JH7110_SYSCLK_JPEGC_AXI, "jpegc_axi", 16, JH7110_SYSCLK_PLL2_OUT),
    186. 

  186. +	JH71X0_GATE(JH7110_SYSCLK_CODAJ12_AXI, "codaj12_axi", 0, JH7110_SYSCLK_JPEGC_AXI),
    187. 

  187. +	JH71X0_GDIV(JH7110_SYSCLK_CODAJ12_CORE, "codaj12_core", 0, 16, JH7110_SYSCLK_PLL2_OUT),
    188. 

  188. +	JH71X0_GATE(JH7110_SYSCLK_CODAJ12_APB, "codaj12_apb", 0, JH7110_SYSCLK_APB_BUS),
    189. 

  189. +	/* vdec */
    190. 

  190. +	JH71X0__DIV(JH7110_SYSCLK_VDEC_AXI, "vdec_axi", 7, JH7110_SYSCLK_BUS_ROOT),
    191. 

  191. +	JH71X0_GATE(JH7110_SYSCLK_WAVE511_AXI, "wave511_axi", 0, JH7110_SYSCLK_VDEC_AXI),
    192. 

  192. +	JH71X0_GDIV(JH7110_SYSCLK_WAVE511_BPU, "wave511_bpu", 0, 7, JH7110_SYSCLK_BUS_ROOT),
    193. 

  193. +	JH71X0_GDIV(JH7110_SYSCLK_WAVE511_VCE, "wave511_vce", 0, 7, JH7110_SYSCLK_PLL0_OUT),
    194. 

  194. +	JH71X0_GATE(JH7110_SYSCLK_WAVE511_APB, "wave511_apb", 0, JH7110_SYSCLK_APB_BUS),
    195. 

  195. +	JH71X0_GATE(JH7110_SYSCLK_VDEC_JPG, "vdec_jpg", 0, JH7110_SYSCLK_JPEGC_AXI),
    196. 

  196. +	JH71X0_GATE(JH7110_SYSCLK_VDEC_MAIN, "vdec_main", 0, JH7110_SYSCLK_VDEC_AXI),
    197. 

  197. +	JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_VDEC_AXI, "noc_bus_vdec_axi", 0, JH7110_SYSCLK_VDEC_AXI),
    198. 

  198. +	/* venc */
    199. 

  199. +	JH71X0__DIV(JH7110_SYSCLK_VENC_AXI, "venc_axi", 15, JH7110_SYSCLK_PLL2_OUT),
    200. 

  200. +	JH71X0_GATE(JH7110_SYSCLK_WAVE420L_AXI, "wave420l_axi", 0, JH7110_SYSCLK_VENC_AXI),
    201. 

  201. +	JH71X0_GDIV(JH7110_SYSCLK_WAVE420L_BPU, "wave420l_bpu", 0, 15, JH7110_SYSCLK_PLL2_OUT),
    202. 

  202. +	JH71X0_GDIV(JH7110_SYSCLK_WAVE420L_VCE, "wave420l_vce", 0, 15, JH7110_SYSCLK_PLL2_OUT),
    203. 

  203. +	JH71X0_GATE(JH7110_SYSCLK_WAVE420L_APB, "wave420l_apb", 0, JH7110_SYSCLK_APB_BUS),
    204. 

  204. +	JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_VENC_AXI, "noc_bus_venc_axi", 0, JH7110_SYSCLK_VENC_AXI),
    205. 

  205. +	/* axi_cfg0 */
    206. 

  206. +	JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN_DIV, "axi_cfg0_main_div", CLK_IS_CRITICAL,
    207. 

  207. +		    JH7110_SYSCLK_AHB1),
    208. 

  208. +	JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN, "axi_cfg0_main", CLK_IS_CRITICAL,
    209. 

  209. +		    JH7110_SYSCLK_AXI_CFG0),
    210. 

  210. +	JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_HIFI4, "axi_cfg0_hifi4", CLK_IS_CRITICAL,
    211. 

  211. +		    JH7110_SYSCLK_HIFI4_AXI),
    212. 

  212. +	/* intmem */
    213. 

  213. +	JH71X0_GATE(JH7110_SYSCLK_AXIMEM2_AXI, "aximem2_axi", 0, JH7110_SYSCLK_AXI_CFG0),
    214. 

  214. +	/* qspi */
    215. 

  215. +	JH71X0_GATE(JH7110_SYSCLK_QSPI_AHB, "qspi_ahb", 0, JH7110_SYSCLK_AHB1),
    216. 

  216. +	JH71X0_GATE(JH7110_SYSCLK_QSPI_APB, "qspi_apb", 0, JH7110_SYSCLK_APB_BUS),
    217. 

  217. +	JH71X0__DIV(JH7110_SYSCLK_QSPI_REF_SRC, "qspi_ref_src", 16, JH7110_SYSCLK_PLL0_OUT),
    218. 

  218. +	JH71X0_GMUX(JH7110_SYSCLK_QSPI_REF, "qspi_ref", 0, 2,
    219. 

  219. +		    JH7110_SYSCLK_OSC,
    220. 

  220. +		    JH7110_SYSCLK_QSPI_REF_SRC),
    221. 

  221. +	/* sdio */
    222. 

  222. +	JH71X0_GATE(JH7110_SYSCLK_SDIO0_AHB, "sdio0_ahb", 0, JH7110_SYSCLK_AHB0),
    223. 

  223. +	JH71X0_GATE(JH7110_SYSCLK_SDIO1_AHB, "sdio1_ahb", 0, JH7110_SYSCLK_AHB0),
    224. 

  224. +	JH71X0_GDIV(JH7110_SYSCLK_SDIO0_SDCARD, "sdio0_sdcard", 0, 15, JH7110_SYSCLK_AXI_CFG0),
    225. 

  225. +	JH71X0_GDIV(JH7110_SYSCLK_SDIO1_SDCARD, "sdio1_sdcard", 0, 15, JH7110_SYSCLK_AXI_CFG0),
    226. 

  226. +	/* stg */
    227. 

  227. +	JH71X0__DIV(JH7110_SYSCLK_USB_125M, "usb_125m", 15, JH7110_SYSCLK_PLL0_OUT),
    228. 

  228. +	JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_STG_AXI, "noc_bus_stg_axi", CLK_IS_CRITICAL,
    229. 

  229. +		    JH7110_SYSCLK_NOCSTG_BUS),
    230. 

  230. +	/* gmac1 */
    231. 

  231. +	JH71X0_GATE(JH7110_SYSCLK_GMAC1_AHB, "gmac1_ahb", 0, JH7110_SYSCLK_AHB0),
    232. 

  232. +	JH71X0_GATE(JH7110_SYSCLK_GMAC1_AXI, "gmac1_axi", 0, JH7110_SYSCLK_STG_AXIAHB),
    233. 

  233. +	JH71X0__DIV(JH7110_SYSCLK_GMAC_SRC, "gmac_src", 7, JH7110_SYSCLK_PLL0_OUT),
    234. 

  234. +	JH71X0__DIV(JH7110_SYSCLK_GMAC1_GTXCLK, "gmac1_gtxclk", 15, JH7110_SYSCLK_PLL0_OUT),
    235. 

  235. +	JH71X0__DIV(JH7110_SYSCLK_GMAC1_RMII_RTX, "gmac1_rmii_rtx", 30,
    236. 

  236. +		    JH7110_SYSCLK_GMAC1_RMII_REFIN),
    237. 

  237. +	JH71X0_GDIV(JH7110_SYSCLK_GMAC1_PTP, "gmac1_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC),
    238. 

  238. +	JH71X0__MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", 2,
    239. 

  239. +		    JH7110_SYSCLK_GMAC1_RGMII_RXIN,
    240. 

  240. +		    JH7110_SYSCLK_GMAC1_RMII_RTX),
    241. 

  241. +	JH71X0__INV(JH7110_SYSCLK_GMAC1_RX_INV, "gmac1_rx_inv", JH7110_SYSCLK_GMAC1_RX),
    242. 

  242. +	JH71X0_GMUX(JH7110_SYSCLK_GMAC1_TX, "gmac1_tx",
    243. 

  243. +		    CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2,
    244. 

  244. +		    JH7110_SYSCLK_GMAC1_GTXCLK,
    245. 

  245. +		    JH7110_SYSCLK_GMAC1_RMII_RTX),
    246. 

  246. +	JH71X0__INV(JH7110_SYSCLK_GMAC1_TX_INV, "gmac1_tx_inv", JH7110_SYSCLK_GMAC1_TX),
    247. 

  247. +	JH71X0_GATE(JH7110_SYSCLK_GMAC1_GTXC, "gmac1_gtxc", 0, JH7110_SYSCLK_GMAC1_GTXCLK),
    248. 

  248. +	/* gmac0 */
    249. 

  249. +	JH71X0_GDIV(JH7110_SYSCLK_GMAC0_GTXCLK, "gmac0_gtxclk", 0, 15, JH7110_SYSCLK_PLL0_OUT),
    250. 

  250. +	JH71X0_GDIV(JH7110_SYSCLK_GMAC0_PTP, "gmac0_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC),
    251. 

  251. +	JH71X0_GDIV(JH7110_SYSCLK_GMAC_PHY, "gmac_phy", 0, 31, JH7110_SYSCLK_GMAC_SRC),
    252. 

  252. +	JH71X0_GATE(JH7110_SYSCLK_GMAC0_GTXC, "gmac0_gtxc", 0, JH7110_SYSCLK_GMAC0_GTXCLK),
    253. 

  253. +	/* apb misc */
    254. 

  254. +	JH71X0_GATE(JH7110_SYSCLK_IOMUX_APB, "iomux_apb", 0, JH7110_SYSCLK_APB_BUS),
    255. 

  255. +	JH71X0_GATE(JH7110_SYSCLK_MAILBOX_APB, "mailbox_apb", 0, JH7110_SYSCLK_APB_BUS),
    256. 

  256. +	JH71X0_GATE(JH7110_SYSCLK_INT_CTRL_APB, "int_ctrl_apb", 0, JH7110_SYSCLK_APB_BUS),
    257. 

  257. +	/* can0 */
    258. 

  258. +	JH71X0_GATE(JH7110_SYSCLK_CAN0_APB, "can0_apb", 0, JH7110_SYSCLK_APB_BUS),
    259. 

  259. +	JH71X0_GDIV(JH7110_SYSCLK_CAN0_TIMER, "can0_timer", 0, 24, JH7110_SYSCLK_OSC),
    260. 

  260. +	JH71X0_GDIV(JH7110_SYSCLK_CAN0_CAN, "can0_can", 0, 63, JH7110_SYSCLK_PERH_ROOT),
    261. 

  261. +	/* can1 */
    262. 

  262. +	JH71X0_GATE(JH7110_SYSCLK_CAN1_APB, "can1_apb", 0, JH7110_SYSCLK_APB_BUS),
    263. 

  263. +	JH71X0_GDIV(JH7110_SYSCLK_CAN1_TIMER, "can1_timer", 0, 24, JH7110_SYSCLK_OSC),
    264. 

  264. +	JH71X0_GDIV(JH7110_SYSCLK_CAN1_CAN, "can1_can", 0, 63, JH7110_SYSCLK_PERH_ROOT),
    265. 

  265. +	/* pwm */
    266. 

  266. +	JH71X0_GATE(JH7110_SYSCLK_PWM_APB, "pwm_apb", 0, JH7110_SYSCLK_APB_BUS),
    267. 

  267. +	/* wdt */
    268. 

  268. +	JH71X0_GATE(JH7110_SYSCLK_WDT_APB, "wdt_apb", 0, JH7110_SYSCLK_APB_BUS),
    269. 

  269. +	JH71X0_GATE(JH7110_SYSCLK_WDT_CORE, "wdt_core", 0, JH7110_SYSCLK_OSC),
    270. 

  270. +	/* timer */
    271. 

  271. +	JH71X0_GATE(JH7110_SYSCLK_TIMER_APB, "timer_apb", 0, JH7110_SYSCLK_APB_BUS),
    272. 

  272. +	JH71X0_GATE(JH7110_SYSCLK_TIMER0, "timer0", 0, JH7110_SYSCLK_OSC),
    273. 

  273. +	JH71X0_GATE(JH7110_SYSCLK_TIMER1, "timer1", 0, JH7110_SYSCLK_OSC),
    274. 

  274. +	JH71X0_GATE(JH7110_SYSCLK_TIMER2, "timer2", 0, JH7110_SYSCLK_OSC),
    275. 

  275. +	JH71X0_GATE(JH7110_SYSCLK_TIMER3, "timer3", 0, JH7110_SYSCLK_OSC),
    276. 

  276. +	/* temp sensor */
    277. 

  277. +	JH71X0_GATE(JH7110_SYSCLK_TEMP_APB, "temp_apb", 0, JH7110_SYSCLK_APB_BUS),
    278. 

  278. +	JH71X0_GDIV(JH7110_SYSCLK_TEMP_CORE, "temp_core", 0, 24, JH7110_SYSCLK_OSC),
    279. 

  279. +	/* spi */
    280. 

  280. +	JH71X0_GATE(JH7110_SYSCLK_SPI0_APB, "spi0_apb", 0, JH7110_SYSCLK_APB0),
    281. 

  281. +	JH71X0_GATE(JH7110_SYSCLK_SPI1_APB, "spi1_apb", 0, JH7110_SYSCLK_APB0),
    282. 

  282. +	JH71X0_GATE(JH7110_SYSCLK_SPI2_APB, "spi2_apb", 0, JH7110_SYSCLK_APB0),
    283. 

  283. +	JH71X0_GATE(JH7110_SYSCLK_SPI3_APB, "spi3_apb", 0, JH7110_SYSCLK_APB_BUS),
    284. 

  284. +	JH71X0_GATE(JH7110_SYSCLK_SPI4_APB, "spi4_apb", 0, JH7110_SYSCLK_APB_BUS),
    285. 

  285. +	JH71X0_GATE(JH7110_SYSCLK_SPI5_APB, "spi5_apb", 0, JH7110_SYSCLK_APB_BUS),
    286. 

  286. +	JH71X0_GATE(JH7110_SYSCLK_SPI6_APB, "spi6_apb", 0, JH7110_SYSCLK_APB_BUS),
    287. 

  287. +	/* i2c */
    288. 

  288. +	JH71X0_GATE(JH7110_SYSCLK_I2C0_APB, "i2c0_apb", 0, JH7110_SYSCLK_APB0),
    289. 

  289. +	JH71X0_GATE(JH7110_SYSCLK_I2C1_APB, "i2c1_apb", 0, JH7110_SYSCLK_APB0),
    290. 

  290. +	JH71X0_GATE(JH7110_SYSCLK_I2C2_APB, "i2c2_apb", 0, JH7110_SYSCLK_APB0),
    291. 

  291. +	JH71X0_GATE(JH7110_SYSCLK_I2C3_APB, "i2c3_apb", 0, JH7110_SYSCLK_APB_BUS),
    292. 

  292. +	JH71X0_GATE(JH7110_SYSCLK_I2C4_APB, "i2c4_apb", 0, JH7110_SYSCLK_APB_BUS),
    293. 

  293. +	JH71X0_GATE(JH7110_SYSCLK_I2C5_APB, "i2c5_apb", 0, JH7110_SYSCLK_APB_BUS),
    294. 

  294. +	JH71X0_GATE(JH7110_SYSCLK_I2C6_APB, "i2c6_apb", 0, JH7110_SYSCLK_APB_BUS),
    295. 

  295. +	/* uart */
    296. 

  296. +	JH71X0_GATE(JH7110_SYSCLK_UART0_APB, "uart0_apb", 0, JH7110_SYSCLK_APB0),
    297. 

  297. +	JH71X0_GATE(JH7110_SYSCLK_UART0_CORE, "uart0_core", 0, JH7110_SYSCLK_OSC),
    298. 

  298. +	JH71X0_GATE(JH7110_SYSCLK_UART1_APB, "uart1_apb", 0, JH7110_SYSCLK_APB0),
    299. 

  299. +	JH71X0_GATE(JH7110_SYSCLK_UART1_CORE, "uart1_core", 0, JH7110_SYSCLK_OSC),
    300. 

  300. +	JH71X0_GATE(JH7110_SYSCLK_UART2_APB, "uart2_apb", 0, JH7110_SYSCLK_APB0),
    301. 

  301. +	JH71X0_GATE(JH7110_SYSCLK_UART2_CORE, "uart2_core", 0, JH7110_SYSCLK_OSC),
    302. 

  302. +	JH71X0_GATE(JH7110_SYSCLK_UART3_APB, "uart3_apb", 0, JH7110_SYSCLK_APB0),
    303. 

  303. +	JH71X0_GDIV(JH7110_SYSCLK_UART3_CORE, "uart3_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
    304. 

  304. +	JH71X0_GATE(JH7110_SYSCLK_UART4_APB, "uart4_apb", 0, JH7110_SYSCLK_APB0),
    305. 

  305. +	JH71X0_GDIV(JH7110_SYSCLK_UART4_CORE, "uart4_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
    306. 

  306. +	JH71X0_GATE(JH7110_SYSCLK_UART5_APB, "uart5_apb", 0, JH7110_SYSCLK_APB0),
    307. 

  307. +	JH71X0_GDIV(JH7110_SYSCLK_UART5_CORE, "uart5_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
    308. 

  308. +	/* pwmdac */
    309. 

  309. +	JH71X0_GATE(JH7110_SYSCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7110_SYSCLK_APB0),
    310. 

  310. +	JH71X0_GDIV(JH7110_SYSCLK_PWMDAC_CORE, "pwmdac_core", 0, 256, JH7110_SYSCLK_AUDIO_ROOT),
    311. 

  311. +	/* spdif */
    312. 

  312. +	JH71X0_GATE(JH7110_SYSCLK_SPDIF_APB, "spdif_apb", 0, JH7110_SYSCLK_APB0),
    313. 

  313. +	JH71X0_GATE(JH7110_SYSCLK_SPDIF_CORE, "spdif_core", 0, JH7110_SYSCLK_MCLK),
    314. 

  314. +	/* i2stx0 */
    315. 

  315. +	JH71X0_GATE(JH7110_SYSCLK_I2STX0_APB, "i2stx0_apb", 0, JH7110_SYSCLK_APB0),
    316. 

  316. +	JH71X0_GDIV(JH7110_SYSCLK_I2STX0_BCLK_MST, "i2stx0_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK),
    317. 

  317. +	JH71X0__INV(JH7110_SYSCLK_I2STX0_BCLK_MST_INV, "i2stx0_bclk_mst_inv",
    318. 

  318. +		    JH7110_SYSCLK_I2STX0_BCLK_MST),
    319. 

  319. +	JH71X0_MDIV(JH7110_SYSCLK_I2STX0_LRCK_MST, "i2stx0_lrck_mst", 64, 2,
    320. 

  320. +		    JH7110_SYSCLK_I2STX0_BCLK_MST_INV,
    321. 

  321. +		    JH7110_SYSCLK_I2STX0_BCLK_MST),
    322. 

  322. +	JH71X0__MUX(JH7110_SYSCLK_I2STX0_BCLK, "i2stx0_bclk",	2,
    323. 

  323. +		    JH7110_SYSCLK_I2STX0_BCLK_MST,
    324. 

  324. +		    JH7110_SYSCLK_I2STX_BCLK_EXT),
    325. 

  325. +	JH71X0__INV(JH7110_SYSCLK_I2STX0_BCLK_INV, "i2stx0_bclk_inv", JH7110_SYSCLK_I2STX0_BCLK),
    326. 

  326. +	JH71X0__MUX(JH7110_SYSCLK_I2STX0_LRCK, "i2stx0_lrck", 2,
    327. 

  327. +		    JH7110_SYSCLK_I2STX0_LRCK_MST,
    328. 

  328. +		    JH7110_SYSCLK_I2STX_LRCK_EXT),
    329. 

  329. +	/* i2stx1 */
    330. 

  330. +	JH71X0_GATE(JH7110_SYSCLK_I2STX1_APB, "i2stx1_apb", 0, JH7110_SYSCLK_APB0),
    331. 

  331. +	JH71X0_GDIV(JH7110_SYSCLK_I2STX1_BCLK_MST, "i2stx1_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK),
    332. 

  332. +	JH71X0__INV(JH7110_SYSCLK_I2STX1_BCLK_MST_INV, "i2stx1_bclk_mst_inv",
    333. 

  333. +		    JH7110_SYSCLK_I2STX1_BCLK_MST),
    334. 

  334. +	JH71X0_MDIV(JH7110_SYSCLK_I2STX1_LRCK_MST, "i2stx1_lrck_mst", 64, 2,
    335. 

  335. +		    JH7110_SYSCLK_I2STX1_BCLK_MST_INV,
    336. 

  336. +		    JH7110_SYSCLK_I2STX1_BCLK_MST),
    337. 

  337. +	JH71X0__MUX(JH7110_SYSCLK_I2STX1_BCLK, "i2stx1_bclk", 2,
    338. 

  338. +		    JH7110_SYSCLK_I2STX1_BCLK_MST,
    339. 

  339. +		    JH7110_SYSCLK_I2STX_BCLK_EXT),
    340. 

  340. +	JH71X0__INV(JH7110_SYSCLK_I2STX1_BCLK_INV, "i2stx1_bclk_inv", JH7110_SYSCLK_I2STX1_BCLK),
    341. 

  341. +	JH71X0__MUX(JH7110_SYSCLK_I2STX1_LRCK, "i2stx1_lrck", 2,
    342. 

  342. +		    JH7110_SYSCLK_I2STX1_LRCK_MST,
    343. 

  343. +		    JH7110_SYSCLK_I2STX_LRCK_EXT),
    344. 

  344. +	/* i2srx */
    345. 

  345. +	JH71X0_GATE(JH7110_SYSCLK_I2SRX_APB, "i2srx_apb", 0, JH7110_SYSCLK_APB0),
    346. 

  346. +	JH71X0_GDIV(JH7110_SYSCLK_I2SRX_BCLK_MST, "i2srx_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK),
    347. 

  347. +	JH71X0__INV(JH7110_SYSCLK_I2SRX_BCLK_MST_INV, "i2srx_bclk_mst_inv",
    348. 

  348. +		    JH7110_SYSCLK_I2SRX_BCLK_MST),
    349. 

  349. +	JH71X0_MDIV(JH7110_SYSCLK_I2SRX_LRCK_MST, "i2srx_lrck_mst", 64, 2,
    350. 

  350. +		    JH7110_SYSCLK_I2SRX_BCLK_MST_INV,
    351. 

  351. +		    JH7110_SYSCLK_I2SRX_BCLK_MST),
    352. 

  352. +	JH71X0__MUX(JH7110_SYSCLK_I2SRX_BCLK, "i2srx_bclk", 2,
    353. 

  353. +		    JH7110_SYSCLK_I2SRX_BCLK_MST,
    354. 

  354. +		    JH7110_SYSCLK_I2SRX_BCLK_EXT),
    355. 

  355. +	JH71X0__INV(JH7110_SYSCLK_I2SRX_BCLK_INV, "i2srx_bclk_inv", JH7110_SYSCLK_I2SRX_BCLK),
    356. 

  356. +	JH71X0__MUX(JH7110_SYSCLK_I2SRX_LRCK, "i2srx_lrck", 2,
    357. 

  357. +		    JH7110_SYSCLK_I2SRX_LRCK_MST,
    358. 

  358. +		    JH7110_SYSCLK_I2SRX_LRCK_EXT),
    359. 

  359. +	/* pdm */
    360. 

  360. +	JH71X0_GDIV(JH7110_SYSCLK_PDM_DMIC, "pdm_dmic", 0, 64, JH7110_SYSCLK_MCLK),
    361. 

  361. +	JH71X0_GATE(JH7110_SYSCLK_PDM_APB, "pdm_apb", 0, JH7110_SYSCLK_APB0),
    362. 

  362. +	/* tdm */
    363. 

  363. +	JH71X0_GATE(JH7110_SYSCLK_TDM_AHB, "tdm_ahb", 0, JH7110_SYSCLK_AHB0),
    364. 

  364. +	JH71X0_GATE(JH7110_SYSCLK_TDM_APB, "tdm_apb", 0, JH7110_SYSCLK_APB0),
    365. 

  365. +	JH71X0_GDIV(JH7110_SYSCLK_TDM_INTERNAL, "tdm_internal", 0, 64, JH7110_SYSCLK_MCLK),
    366. 

  366. +	JH71X0__MUX(JH7110_SYSCLK_TDM_TDM, "tdm_tdm", 2,
    367. 

  367. +		    JH7110_SYSCLK_TDM_INTERNAL,
    368. 

  368. +		    JH7110_SYSCLK_TDM_EXT),
    369. 

  369. +	JH71X0__INV(JH7110_SYSCLK_TDM_TDM_INV, "tdm_tdm_inv", JH7110_SYSCLK_TDM_TDM),
    370. 

  370. +	/* jtag */
    371. 

  371. +	JH71X0__DIV(JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG, "jtag_certification_trng", 4,
    372. 

  372. +		    JH7110_SYSCLK_OSC),
    373. 

  373. +};
    374. 

  374. +
    375. 

  375. +static struct clk_hw *jh7110_sysclk_get(struct of_phandle_args *clkspec, void *data)
    376. 

  376. +{
    377. 

  377. +	struct jh71x0_clk_priv *priv = data;
    378. 

  378. +	unsigned int idx = clkspec->args[0];
    379. 

  379. +
    380. 

  380. +	if (idx < JH7110_SYSCLK_END)
    381. 

  381. +		return &priv->reg[idx].hw;
    382. 

  382. +
    383. 

  383. +	return ERR_PTR(-EINVAL);
    384. 

  384. +}
    385. 

  385. +
    386. 

  386. +static void jh7110_reset_unregister_adev(void *_adev)
    387. 

  387. +{
    388. 

  388. +	struct auxiliary_device *adev = _adev;
    389. 

  389. +
    390. 

  390. +	auxiliary_device_delete(adev);
    391. 

  391. +}
    392. 

  392. +
    393. 

  393. +static void jh7110_reset_adev_release(struct device *dev)
    394. 

  394. +{
    395. 

  395. +	struct auxiliary_device *adev = to_auxiliary_dev(dev);
    396. 

  396. +
    397. 

  397. +	auxiliary_device_uninit(adev);
    398. 

  398. +}
    399. 

  399. +
    400. 

  400. +int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
    401. 

  401. +				     const char *adev_name,
    402. 

  402. +				     u32 adev_id)
    403. 

  403. +{
    404. 

  404. +	struct auxiliary_device *adev;
    405. 

  405. +	int ret;
    406. 

  406. +
    407. 

  407. +	adev = devm_kzalloc(priv->dev, sizeof(*adev), GFP_KERNEL);
    408. 

  408. +	if (!adev)
    409. 

  409. +		return -ENOMEM;
    410. 

  410. +
    411. 

  411. +	adev->name = adev_name;
    412. 

  412. +	adev->dev.parent = priv->dev;
    413. 

  413. +	adev->dev.release = jh7110_reset_adev_release;
    414. 

  414. +	adev->id = adev_id;
    415. 

  415. +
    416. 

  416. +	ret = auxiliary_device_init(adev);
    417. 

  417. +	if (ret)
    418. 

  418. +		return ret;
    419. 

  419. +
    420. 

  420. +	ret = auxiliary_device_add(adev);
    421. 

  421. +	if (ret) {
    422. 

  422. +		auxiliary_device_uninit(adev);
    423. 

  423. +		return ret;
    424. 

  424. +	}
    425. 

  425. +
    426. 

  426. +	return devm_add_action_or_reset(priv->dev,
    427. 

  427. +					jh7110_reset_unregister_adev, adev);
    428. 

  428. +}
    429. 

  429. +EXPORT_SYMBOL_GPL(jh7110_reset_controller_register);
    430. 

  430. +
    431. 

  431. +static int __init jh7110_syscrg_probe(struct platform_device *pdev)
    432. 

  432. +{
    433. 

  433. +	struct jh71x0_clk_priv *priv;
    434. 

  434. +	unsigned int idx;
    435. 

  435. +	int ret;
    436. 

  436. +
    437. 

  437. +	priv = devm_kzalloc(&pdev->dev,
    438. 

  438. +			    struct_size(priv, reg, JH7110_SYSCLK_END),
    439. 

  439. +			    GFP_KERNEL);
    440. 

  440. +	if (!priv)
    441. 

  441. +		return -ENOMEM;
    442. 

  442. +
    443. 

  443. +	spin_lock_init(&priv->rmw_lock);
    444. 

  444. +	priv->dev = &pdev->dev;
    445. 

  445. +	priv->base = devm_platform_ioremap_resource(pdev, 0);
    446. 

  446. +	if (IS_ERR(priv->base))
    447. 

  447. +		return PTR_ERR(priv->base);
    448. 

  448. +
    449. 

  449. +	dev_set_drvdata(priv->dev, (void *)(&priv->base));
    450. 

  450. +
    451. 

  451. +	/*
    452. 

  452. +	 * These PLL clocks are not actually fixed factor clocks and can be
    453. 

  453. +	 * controlled by the syscon registers of JH7110. They will be dropped
    454. 

  454. +	 * and registered in the PLL clock driver instead.
    455. 

  455. +	 */
    456. 

  456. +	/* 24MHz -> 1000.0MHz */
    457. 

  457. +	priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out",
    458. 

  458. +							 "osc", 0, 125, 3);
    459. 

  459. +	if (IS_ERR(priv->pll[0]))
    460. 

  460. +		return PTR_ERR(priv->pll[0]);
    461. 

  461. +
    462. 

  462. +	/* 24MHz -> 1066.0MHz */
    463. 

  463. +	priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out",
    464. 

  464. +							 "osc", 0, 533, 12);
    465. 

  465. +	if (IS_ERR(priv->pll[1]))
    466. 

  466. +		return PTR_ERR(priv->pll[1]);
    467. 

  467. +
    468. 

  468. +	/* 24MHz -> 1188.0MHz */
    469. 

  469. +	priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out",
    470. 

  470. +							 "osc", 0, 99, 2);
    471. 

  471. +	if (IS_ERR(priv->pll[2]))
    472. 

  472. +		return PTR_ERR(priv->pll[2]);
    473. 

  473. +
    474. 

  474. +	for (idx = 0; idx < JH7110_SYSCLK_END; idx++) {
    475. 

  475. +		u32 max = jh7110_sysclk_data[idx].max;
    476. 

  476. +		struct clk_parent_data parents[4] = {};
    477. 

  477. +		struct clk_init_data init = {
    478. 

  478. +			.name = jh7110_sysclk_data[idx].name,
    479. 

  479. +			.ops = starfive_jh71x0_clk_ops(max),
    480. 

  480. +			.parent_data = parents,
    481. 

  481. +			.num_parents =
    482. 

  482. +				((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
    483. 

  483. +			.flags = jh7110_sysclk_data[idx].flags,
    484. 

  484. +		};
    485. 

  485. +		struct jh71x0_clk *clk = &priv->reg[idx];
    486. 

  486. +		unsigned int i;
    487. 

  487. +
    488. 

  488. +		for (i = 0; i < init.num_parents; i++) {
    489. 

  489. +			unsigned int pidx = jh7110_sysclk_data[idx].parents[i];
    490. 

  490. +
    491. 

  491. +			if (pidx < JH7110_SYSCLK_END)
    492. 

  492. +				parents[i].hw = &priv->reg[pidx].hw;
    493. 

  493. +			else if (pidx == JH7110_SYSCLK_OSC)
    494. 

  494. +				parents[i].fw_name = "osc";
    495. 

  495. +			else if (pidx == JH7110_SYSCLK_GMAC1_RMII_REFIN)
    496. 

  496. +				parents[i].fw_name = "gmac1_rmii_refin";
    497. 

  497. +			else if (pidx == JH7110_SYSCLK_GMAC1_RGMII_RXIN)
    498. 

  498. +				parents[i].fw_name = "gmac1_rgmii_rxin";
    499. 

  499. +			else if (pidx == JH7110_SYSCLK_I2STX_BCLK_EXT)
    500. 

  500. +				parents[i].fw_name = "i2stx_bclk_ext";
    501. 

  501. +			else if (pidx == JH7110_SYSCLK_I2STX_LRCK_EXT)
    502. 

  502. +				parents[i].fw_name = "i2stx_lrck_ext";
    503. 

  503. +			else if (pidx == JH7110_SYSCLK_I2SRX_BCLK_EXT)
    504. 

  504. +				parents[i].fw_name = "i2srx_bclk_ext";
    505. 

  505. +			else if (pidx == JH7110_SYSCLK_I2SRX_LRCK_EXT)
    506. 

  506. +				parents[i].fw_name = "i2srx_lrck_ext";
    507. 

  507. +			else if (pidx == JH7110_SYSCLK_TDM_EXT)
    508. 

  508. +				parents[i].fw_name = "tdm_ext";
    509. 

  509. +			else if (pidx == JH7110_SYSCLK_MCLK_EXT)
    510. 

  510. +				parents[i].fw_name = "mclk_ext";
    511. 

  511. +			else
    512. 

  512. +				parents[i].hw = priv->pll[pidx - JH7110_SYSCLK_PLL0_OUT];
    513. 

  513. +		}
    514. 

  514. +
    515. 

  515. +		clk->hw.init = &init;
    516. 

  516. +		clk->idx = idx;
    517. 

  517. +		clk->max_div = max & JH71X0_CLK_DIV_MASK;
    518. 

  518. +
    519. 

  519. +		ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
    520. 

  520. +		if (ret)
    521. 

  521. +			return ret;
    522. 

  522. +	}
    523. 

  523. +
    524. 

  524. +	ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_sysclk_get, priv);
    525. 

  525. +	if (ret)
    526. 

  526. +		return ret;
    527. 

  527. +
    528. 

  528. +	return jh7110_reset_controller_register(priv, "rst-sys", 0);
    529. 

  529. +}
    530. 

  530. +
    531. 

  531. +static const struct of_device_id jh7110_syscrg_match[] = {
    532. 

  532. +	{ .compatible = "starfive,jh7110-syscrg" },
    533. 

  533. +	{ /* sentinel */ }
    534. 

  534. +};
    535. 

  535. +
    536. 

  536. +static struct platform_driver jh7110_syscrg_driver = {
    537. 

  537. +	.driver = {
    538. 

  538. +		.name = "clk-starfive-jh7110-sys",
    539. 

  539. +		.of_match_table = jh7110_syscrg_match,
    540. 

  540. +		.suppress_bind_attrs = true,
    541. 

  541. +	},
    542. 

  542. +};
    543. 

  543. +builtin_platform_driver_probe(jh7110_syscrg_driver, jh7110_syscrg_probe);
    544. 

  544. --- /dev/null
    545. 

  545. +++ b/drivers/clk/starfive/clk-starfive-jh7110.h
    546. 

  546. @@ -0,0 +1,11 @@
    547. 

  547. +/* SPDX-License-Identifier: GPL-2.0 */
    548. 

  548. +#ifndef __CLK_STARFIVE_JH7110_H
    549. 

  549. +#define __CLK_STARFIVE_JH7110_H
    550. 

  550. +
    551. 

  551. +#include "clk-starfive-jh71x0.h"
    552. 

  552. +
    553. 

  553. +int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
    554. 

  554. +				     const char *adev_name,
    555. 

  555. +				     u32 adev_id);
    556. 

  556. +
    557. 

  557. +#endif
    558.