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- From 514cae455122c799638226f4358e8e6f5e155248 Mon Sep 17 00:00:00 2001
- From: Jianlong Huang <[email protected]>
- Date: Thu, 9 Feb 2023 22:37:00 +0800
- Subject: [PATCH 027/122] dt-bindings: pinctrl: Add StarFive JH7110 aon pinctrl
- Add pinctrl bindings for StarFive JH7110 SoC aon pinctrl controller.
- Reviewed-by: Rob Herring <[email protected]>
- Signed-off-by: Jianlong Huang <[email protected]>
- Co-developed-by: Emil Renner Berthing <[email protected]>
- Signed-off-by: Emil Renner Berthing <[email protected]>
- Signed-off-by: Hal Feng <[email protected]>
- ---
- .../pinctrl/starfive,jh7110-aon-pinctrl.yaml | 124 ++++++++++++++++++
- .../pinctrl/starfive,jh7110-pinctrl.h | 22 ++++
- 2 files changed, 146 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml
- --- /dev/null
- +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml
- @@ -0,0 +1,124 @@
- +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
- +%YAML 1.2
- +---
- +$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-aon-pinctrl.yaml#
- +$schema: http://devicetree.org/meta-schemas/core.yaml#
- +
- +title: StarFive JH7110 AON Pin Controller
- +
- +description: |
- + Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
- +
- + Out of the SoC's many pins only the ones named PAD_RGPIO0 to PAD_RGPIO3
- + can be multiplexed and have configurable bias, drive strength,
- + schmitt trigger etc.
- + Some peripherals such as PWM have their I/O go through the 4 "GPIOs".
- +
- +maintainers:
- + - Jianlong Huang <[email protected]>
- +
- +properties:
- + compatible:
- + const: starfive,jh7110-aon-pinctrl
- +
- + reg:
- + maxItems: 1
- +
- + resets:
- + maxItems: 1
- +
- + interrupts:
- + maxItems: 1
- +
- + interrupt-controller: true
- +
- + '#interrupt-cells':
- + const: 2
- +
- + gpio-controller: true
- +
- + '#gpio-cells':
- + const: 2
- +
- +patternProperties:
- + '-[0-9]+$':
- + type: object
- + additionalProperties: false
- + patternProperties:
- + '-pins$':
- + type: object
- + description: |
- + A pinctrl node should contain at least one subnode representing the
- + pinctrl groups available on the machine. Each subnode will list the
- + pins it needs, and how they should be configured, with regard to
- + muxer configuration, bias, input enable/disable, input schmitt
- + trigger enable/disable, slew-rate and drive strength.
- + allOf:
- + - $ref: /schemas/pinctrl/pincfg-node.yaml
- + - $ref: /schemas/pinctrl/pinmux-node.yaml
- + additionalProperties: false
- +
- + properties:
- + pinmux:
- + description: |
- + The list of GPIOs and their mux settings that properties in the
- + node apply to. This should be set using the GPIOMUX macro.
- +
- + bias-disable: true
- +
- + bias-pull-up:
- + type: boolean
- +
- + bias-pull-down:
- + type: boolean
- +
- + drive-strength:
- + enum: [ 2, 4, 8, 12 ]
- +
- + input-enable: true
- +
- + input-disable: true
- +
- + input-schmitt-enable: true
- +
- + input-schmitt-disable: true
- +
- + slew-rate:
- + maximum: 1
- +
- +required:
- + - compatible
- + - reg
- + - interrupts
- + - interrupt-controller
- + - '#interrupt-cells'
- + - gpio-controller
- + - '#gpio-cells'
- +
- +additionalProperties: false
- +
- +examples:
- + - |
- + pinctrl@17020000 {
- + compatible = "starfive,jh7110-aon-pinctrl";
- + reg = <0x17020000 0x10000>;
- + resets = <&aoncrg 2>;
- + interrupts = <85>;
- + interrupt-controller;
- + #interrupt-cells = <2>;
- + gpio-controller;
- + #gpio-cells = <2>;
- +
- + pwm-0 {
- + pwm-pins {
- + pinmux = <0xff030802>;
- + bias-disable;
- + drive-strength = <12>;
- + input-disable;
- + input-schmitt-disable;
- + slew-rate = <0>;
- + };
- + };
- + };
- +
- +...
- --- a/include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h
- +++ b/include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h
- @@ -104,6 +104,28 @@
- #define PAD_QSPI_DATA2 93
- #define PAD_QSPI_DATA3 94
-
- +/* aon_iomux pins */
- +#define PAD_TESTEN 0
- +#define PAD_RGPIO0 1
- +#define PAD_RGPIO1 2
- +#define PAD_RGPIO2 3
- +#define PAD_RGPIO3 4
- +#define PAD_RSTN 5
- +#define PAD_GMAC0_MDC 6
- +#define PAD_GMAC0_MDIO 7
- +#define PAD_GMAC0_RXD0 8
- +#define PAD_GMAC0_RXD1 9
- +#define PAD_GMAC0_RXD2 10
- +#define PAD_GMAC0_RXD3 11
- +#define PAD_GMAC0_RXDV 12
- +#define PAD_GMAC0_RXC 13
- +#define PAD_GMAC0_TXD0 14
- +#define PAD_GMAC0_TXD1 15
- +#define PAD_GMAC0_TXD2 16
- +#define PAD_GMAC0_TXD3 17
- +#define PAD_GMAC0_TXEN 18
- +#define PAD_GMAC0_TXC 19
- +
- #define GPOUT_LOW 0
- #define GPOUT_HIGH 1
-
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