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0038-riscv-dts-starfive-jh7110-Add-syscon-nodes.patch 1.6 KB

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  1. From 40098f3d986dc90f6a7be0e5a35ddaccd1ded0b5 Mon Sep 17 00:00:00 2001
  2. From: William Qiu <[email protected]>
  3. Date: Thu, 6 Apr 2023 15:46:34 +0800
  4. Subject: [PATCH 038/122] riscv: dts: starfive: jh7110: Add syscon nodes
  5. Add stg_syscon/sys_syscon/aon_syscon nodes for JH7110 Soc.
  6. Signed-off-by: William Qiu <[email protected]>
  7. Reviewed-by: Conor Dooley <[email protected]>
  8. Reviewed-by: Emil Renner Berthing <[email protected]>
  9. ---
  10. arch/riscv/boot/dts/starfive/jh7110.dtsi | 15 +++++++++++++++
  11. 1 file changed, 15 insertions(+)
  12. --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
  13. +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
  14. @@ -353,6 +353,11 @@
  15. status = "disabled";
  16. };
  17. + stg_syscon: syscon@10240000 {
  18. + compatible = "starfive,jh7110-stg-syscon", "syscon";
  19. + reg = <0x0 0x10240000 0x0 0x1000>;
  20. + };
  21. +
  22. uart3: serial@12000000 {
  23. compatible = "snps,dw-apb-uart";
  24. reg = <0x0 0x12000000 0x0 0x10000>;
  25. @@ -457,6 +462,11 @@
  26. #reset-cells = <1>;
  27. };
  28. + sys_syscon: syscon@13030000 {
  29. + compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
  30. + reg = <0x0 0x13030000 0x0 0x1000>;
  31. + };
  32. +
  33. sysgpio: pinctrl@13040000 {
  34. compatible = "starfive,jh7110-sys-pinctrl";
  35. reg = <0x0 0x13040000 0x0 0x10000>;
  36. @@ -486,6 +496,11 @@
  37. #reset-cells = <1>;
  38. };
  39. + aon_syscon: syscon@17010000 {
  40. + compatible = "starfive,jh7110-aon-syscon", "syscon", "simple-mfd";
  41. + reg = <0x0 0x17010000 0x0 0x1000>;
  42. + };
  43. +
  44. aongpio: pinctrl@17020000 {
  45. compatible = "starfive,jh7110-aon-pinctrl";
  46. reg = <0x0 0x17020000 0x0 0x10000>;