0046-riscv-dts-starfive-jh7110-Add-ethernet-device-nodes.patch 3.2 KB

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  1. From cad740398f4cb6604abf1ddcc70121b2634ac233 Mon Sep 17 00:00:00 2001
  2. From: Samin Guo <[email protected]>
  3. Date: Fri, 3 Mar 2023 16:49:31 +0800
  4. Subject: [PATCH 046/122] riscv: dts: starfive: jh7110: Add ethernet device
  5. nodes
  6. Add JH7110 ethernet device node to support gmac driver for the JH7110
  7. RISC-V SoC.
  8. Tested-by: Tommaso Merciai <[email protected]>
  9. Signed-off-by: Yanhong Wang <[email protected]>
  10. Signed-off-by: Samin Guo <[email protected]>
  11. ---
  12. arch/riscv/boot/dts/starfive/jh7110.dtsi | 69 ++++++++++++++++++++++++
  13. 1 file changed, 69 insertions(+)
  14. --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
  15. +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
  16. @@ -230,6 +230,13 @@
  17. #clock-cells = <0>;
  18. };
  19. + stmmac_axi_setup: stmmac-axi-config {
  20. + snps,lpi_en;
  21. + snps,wr_osr_lmt = <4>;
  22. + snps,rd_osr_lmt = <4>;
  23. + snps,blen = <256 128 64 32 0 0 0>;
  24. + };
  25. +
  26. tdm_ext: tdm-ext-clock {
  27. compatible = "fixed-clock";
  28. clock-output-names = "tdm_ext";
  29. @@ -489,6 +496,68 @@
  30. #gpio-cells = <2>;
  31. };
  32. + gmac0: ethernet@16030000 {
  33. + compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
  34. + reg = <0x0 0x16030000 0x0 0x10000>;
  35. + clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>,
  36. + <&aoncrg JH7110_AONCLK_GMAC0_AHB>,
  37. + <&syscrg JH7110_SYSCLK_GMAC0_PTP>,
  38. + <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>,
  39. + <&syscrg JH7110_SYSCLK_GMAC0_GTXC>;
  40. + clock-names = "stmmaceth", "pclk", "ptp_ref",
  41. + "tx", "gtx";
  42. + resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>,
  43. + <&aoncrg JH7110_AONRST_GMAC0_AHB>;
  44. + reset-names = "stmmaceth", "ahb";
  45. + interrupts = <7>, <6>, <5>;
  46. + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
  47. + rx-fifo-depth = <2048>;
  48. + tx-fifo-depth = <2048>;
  49. + snps,multicast-filter-bins = <64>;
  50. + snps,perfect-filter-entries = <8>;
  51. + snps,fixed-burst;
  52. + snps,no-pbl-x8;
  53. + snps,force_thresh_dma_mode;
  54. + snps,axi-config = <&stmmac_axi_setup>;
  55. + snps,tso;
  56. + snps,en-tx-lpi-clockgating;
  57. + snps,txpbl = <16>;
  58. + snps,rxpbl = <16>;
  59. + starfive,syscon = <&aon_syscon 0xc 0x12>;
  60. + status = "disabled";
  61. + };
  62. +
  63. + gmac1: ethernet@16040000 {
  64. + compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
  65. + reg = <0x0 0x16040000 0x0 0x10000>;
  66. + clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>,
  67. + <&syscrg JH7110_SYSCLK_GMAC1_AHB>,
  68. + <&syscrg JH7110_SYSCLK_GMAC1_PTP>,
  69. + <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>,
  70. + <&syscrg JH7110_SYSCLK_GMAC1_GTXC>;
  71. + clock-names = "stmmaceth", "pclk", "ptp_ref",
  72. + "tx", "gtx";
  73. + resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>,
  74. + <&syscrg JH7110_SYSRST_GMAC1_AHB>;
  75. + reset-names = "stmmaceth", "ahb";
  76. + interrupts = <78>, <77>, <76>;
  77. + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
  78. + rx-fifo-depth = <2048>;
  79. + tx-fifo-depth = <2048>;
  80. + snps,multicast-filter-bins = <64>;
  81. + snps,perfect-filter-entries = <8>;
  82. + snps,fixed-burst;
  83. + snps,no-pbl-x8;
  84. + snps,force_thresh_dma_mode;
  85. + snps,axi-config = <&stmmac_axi_setup>;
  86. + snps,tso;
  87. + snps,en-tx-lpi-clockgating;
  88. + snps,txpbl = <16>;
  89. + snps,rxpbl = <16>;
  90. + starfive,syscon = <&sys_syscon 0x90 0x2>;
  91. + status = "disabled";
  92. + };
  93. +
  94. aoncrg: clock-controller@17000000 {
  95. compatible = "starfive,jh7110-aoncrg";
  96. reg = <0x0 0x17000000 0x0 0x10000>;